Hello,

I was running through the developing branch. The stable version works.

Thank you,
Giorgos

2015-04-06 16:46 GMT+03:00 Stephan Diestelhorst <
stephan.diestelho...@arm.com>:

> Hi Giorgos,
>
> Am Samstag, 4. April 2015, 20:18:26 schrieb Giorgos Kopanas:
> > I am trying to make Gem5 work with the DVFS as explained in the
> > website. While running in Atomic Simple it is working as intended but
> > when I change the cpu type to arm_detailed the simulation crushes
> > during boot. The message that is shown is the following:
> >
> > gem5.opt: build/ARM/mem/cache/cache_impl.hh:633: bool
> > Cache<TagStore>::recvTimingReq(PacketPtr) [with TagStore = LRU;
> > PacketPtr = Packet*]: Assertion `!pkt->req->isUncacheable()' failed.
> >
> > Has anyone actually ever booted the DVFS enabled kernel that is
> > proposed in the website with arm_detailed cpu type or  is it not
> > supported?
>
> This should work, we certainly use detailed mode together with DVFS.
> There has been quite a bit of work and flux on uncacheable things
> lately, are you running this with the most recent (non-stable) gem5?
>
> If yes, it might also be worthwhile to get try out some of the
> uncacheable patches on RB (search for uncacheable there), and / or
> produce some additional information to get this debugged.
>
> Thanks,
>   Stephan
>
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