Hello Everyone,
Novice gem5 user here. I have been tasked with supporting same-level hybrid cache in gem5, that is, for example, having one STT-RAM L3 cache and one SRAM L3 cache. I have already implemented this patch: <http://reviews.gem5.org/r/1809/> http://reviews.gem5.org/r/1809/ Which allows the differentiation of read and write latencies at the separate cache levels. I am expected to extend this functionality so multiple architectures can be instantiated at the same level of cache. Has this been done or attempted before, and if not does anyone have an idea of how to go about this? Please let me know if I haven't sufficiently outlined what I'm looking to do. Thanks in advance, Bryce
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