Hi Bryce,

A few suggestions and questions:

  1.  Have you rebased on modernised http://reviews.gem5.org/r/1809/? If so, 
could you please post it. As I commented on that patch a year and a half ago…it 
would be good to get this functionality into the codebase.
  2.  gem5 allows you to add as many caches as you want on each level, the 
question is how you want to choose between them. Currently you can either do it 
based on complete ranges e.g. [0:x] for cache0, [x:end] for cache1, or you can 
make use of gem5s interleaving (and hashing) support to have the same overall 
range, but hash some address bits to determine which cache.

Andreas

From: gem5-users 
<[email protected]<mailto:[email protected]>> on behalf of 
Bryce Depperman <[email protected]<mailto:[email protected]>>
Reply-To: gem5 users mailing list 
<[email protected]<mailto:[email protected]>>
Date: Sunday, 13 March 2016 at 20:07
To: "[email protected]<mailto:[email protected]>" 
<[email protected]<mailto:[email protected]>>
Subject: [gem5-users] Same-Level Hybrid Cache in Gem5

Hello Everyone,

Novice gem5 user here. I have been tasked with supporting same-level hybrid 
cache in gem5, that is, for example, having one STT-RAM L3 cache and one SRAM 
L3 cache. I have already implemented this patch:

http://reviews.gem5.org/r/1809/

Which allows the differentiation of read and write latencies at the separate 
cache levels. I am expected to extend this functionality so multiple 
architectures can be instantiated at the same level of cache. Has this been 
done or attempted before, and if not does anyone have an idea of how to go 
about this? Please let me know if I haven't sufficiently outlined what I'm 
looking to do.

Thanks in advance,
Bryce

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