Hello Andreas, Our rebase was on gem5 version 10789 (approximately), so I don't believe it is worth posting.
Can you point me more specifically to where I can instantiate caches with different latency values? I don't have sufficient knowledge of Gem5's structuring to understand what you mean. Where would I specify the complete ranges for cacheX? Or how could I use interleaving and hashing to delineate different caches? I apologize if these are basic questions. Thanks, Bryce Date: Sat, 19 Mar 2016 15:22:38 +0000 From: Andreas Hansson <[email protected]> To: gem5 users mailing list <[email protected]> Subject: Re: [gem5-users] Same-Level Hybrid Cache in Gem5 Message-ID: <d3131e5a.26538%[email protected]> Content-Type: text/plain; charset="utf-8" Hi Bryce, A few suggestions and questions: 1. Have you rebased on modernised http://reviews.gem5.org/r/1809/? If so, could you please post it. As I commented on that patch a year and a half ago…it would be good to get this functionality into the codebase. 2. gem5 allows you to add as many caches as you want on each level, the question is how you want to choose between them. Currently you can either do it based on complete ranges e.g. [0:x] for cache0, [x:end] for cache1, or you can make use of gem5s interleaving (and hashing) support to have the same overall range, but hash some address bits to determine which cache. Andreas From: gem5-users <[email protected]<mailto:[email protected]>> on behalf of Bryce Depperman <[email protected]<mailto:[email protected]>> Reply-To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Sunday, 13 March 2016 at 20:07 To: "[email protected]<mailto:[email protected]>" <[email protected]<mailto:[email protected]>> Subject: [gem5-users] Same-Level Hybrid Cache in Gem5 Hello Everyone, Novice gem5 user here. I have been tasked with supporting same-level hybrid cache in gem5, that is, for example, having one STT-RAM L3 cache and one SRAM L3 cache. I have already implemented this patch: http://reviews.gem5.org/r/1809/ Which allows the differentiation of read and write latencies at the separate cache levels. I am expected to extend this functionality so multiple architectures can be instantiated at the same level of cache. Has this been done or attempted before, and if not does anyone have an idea of how to go about this? Please let me know if I haven't sufficiently outlined what I'm looking to do. Thanks in advance, Bryce _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
