Hello, For a Cortex-A9, most DRAM params may be the same as a DRAM for a PC, but not the size and frequency as Anoir want. The DRAM latency cannot be set explicitly, because it varies depending on several factors and other params (https://en.wikipedia.org/wiki/Memory_timings).
In the DDR4_2400_x64 model, I particularly set the frontend and backend latencies to 0. It gives best and average latencies of 36 and 75 ns for SPEC CPU 2006, which seems to be close to commercial ones. -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-08-23 16:08 GMT+02:00 Jason Lowe-Power <[email protected]>: > Hi Anouar, > > I believe your problem is that you are not using the O3_ARM_v7aRAM object > as the DRAM controller for your system. If you want to use your new class > in the system that you instantiate, you have to instantiate this new class. > I believe that for se.py, the memory controllers are created via the > "config_mem" function in configs/common/MemConfig.py. To tell what options > your system is using, you can check the config.ini file in the outdir. > > Another option, if you want to customize your system significantly, is to > write your own config script like configs/example/arm/fs_bigLITTLE.py or > like in the Learning gem5 tutorial/book: http://www. > lowepower.com/jason/learning_gem5/part1/simple_config.html. > > Finally, I would be surprised if it really made sense to make a new DRAM > controller. The controllers defined in src/mem/DRAMCtrl.py are all > "realistic" (as in the numbers came from datasheets), and I would be > surprised if what you're trying to simulate isn't already defined there. > > Cheers, > Jason > > On Mon, Aug 22, 2016 at 9:52 AM anoir nechi <[email protected]> wrote: > >> I want to set some parameters to use the DRAM with an O3_ARM_v7a >> (cortex-A9), So, I had a look on the src/mem/DRAMCtrl.py and i found the >> parameters that I can play with except for the latency, these are the >> desired parameters: >> >> *Size* = 256 MB >> >> *Clock* = 400 MHz >> >> *Latency* = 65 >> >> and this how I instantiated DRAM in O3_ARM_v7a.py: >> >> #DRAM memoryclass O3_ARM_v7aRAM(DRAMCtrl): >> device_size = '256MB' >> static_frontend_latency = '10ns' >> static_backend_latency = '10ns' >> device_bus_width = 8 >> burst_length = 8 >> device_rowbuffer_size = '1kB' >> devices_per_rank = 8 >> ranks_per_channel = 2 >> banks_per_rank = 8 >> tCK = '0.75ns'# 400MHz >> ... >> >> I kept changing the static latencies but i'm always getting the same memory >> access average latency: >> system.mem_ctrls.avgMemAccLat 21169.35 >> >> this is what i do everytime : >> >> 1) change the parameters in O3_ARM_v7a.py and save it >> >> 2) execute this command: >> build/ARM/gem5.opt configs/example/se.py --cpu-type=detailed -n 1 >> --cpu-clock=800MHz --caches --l2cache -c /home/anoir/workspace/fft/fft >> >> Am I doing something wrong or what? >> can someone help me? >> >> -- >> *Anouar NECHI* >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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