Hello All, I have read a paper titled “Micro-architectural Simulation of In-order and Out-of-order ARM Microprocessors with gem5” where the author modified the O3CPU Instruction Scheduler to issue “inorder” and also disabled the “rename stage”. I am trying to do the same, but don’t know which file/s to look at.
What functions should I look at to start with? Any suggestions would be helpful. Sincerely Monir Zaman
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