Hi Jason,
Thanks for your reply. The "same" architecture in hmctest.py states that
memory range of serial links is same, i.e. whole memory can be accessed by
any of the serial link (which implies all serial link have overlapped
accessible memory ranges, 4GB accessible to all serial links in this
case)...
Here is relevant piece of code from hmctest.py:
# Memmory ranges of serial link for arch-0
# Same as the ranges of vault controllers - 4 vault - to - 1 serial link
if options.arch == "same":
ser_range = [ AddrRange(0, (4 * oneGBytes) - 1)
for i in range(num_serial_links)]
options.ser_ranges = ser_range
It runs fine when i use tgens (4 in total, each connected to separate
serial link), and in hmc_dev, all xbars are connected to each other through
bridges, to properly respond to a request arriving at non-local vault.
But when I connect CPU, L1 and L2 caches and membus instead of tgens, i get
the same error as i mentioned before. According to you, each serial link
should be assigned a different memory range, then how it works with "same"
architecture with tgens and doesn't work with CPU and Caches configuration?
Does it have something to do with membus, because error stated that membus
can't have more than one port responding in same memory range?
Thanks
Muzamil
Message: 4
Date: Fri, 17 Feb 2017 14:29:36 +0000
From: Jason Lowe-Power <[email protected]>
To: gem5 users mailing list <[email protected]>
Subject: Re: [gem5-users] Error in Simulating hmctest.py with CPU
Message-ID:
<CAFEhpUf2b0M5pt+gsOTNuKi1+OZ=fuqsp9t-ytc-zedcakb...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi Muzamil,
On Thu, Feb 16, 2017 at 5:29 PM Muzamil Rafique <[email protected]
>
wrote:
> Hi All,
>
> I was trying to run a simple system consisting of a CPU, L1 and L2 caches
> and HMC as main memory. (Similar to hmctest.py and just replacing traffic
> generators by cpu and adding L1 and L2 caches). While running "same"
> architecture, where all available memory is accessible by all four serial
> links, I am getting the following error:
>
> warn: Cache line size is neither 16, 32, 64 nor 128 bytes.
>
This is a serious warning. You should make sure to fix this.
>
> 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
>
> fatal: system.membus has two ports responding within range [0 :
> 0xffffffff]:
> system.hmc_host.seriallink1.slave
> system.hmc_host.seriallink0.slave
> @ tick 0
> [recvRangeChange:build/X86/mem/xbar.cc, line 428]
>
You should set the memory range on each link to be something different. I
would bet there is some example code in the hmctest.py file, but I haven't
looked close enough to point you to an exact line.
>
>
> I tried to re-run simulation without using caches by connecting cpu icache
> and dcache ports directly to membus, but error still persists.
>
> Any ideas to fix this issue?
>
> Thanks
> Muzamil
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