Hi Marcelo, Yes, gem5 does support the C extension (64-bit version only, though). I don't know what could be causing your particular issue. I'm not sure advancePC is the issue, though, because all that essentially does is call PCState::advance(), which is inherited unchanged from GenericISA::UPCState. Try doing as Jason suggests and run your simulation with the Fetch debug flag enabled, and maybe that will shed some light on the issue.
-Alec On Thu, May 24, 2018 at 7:20 PM, Jason Lowe-Power <ja...@lowepower.com> wrote: > Hi Marcelo, > > I'm not sure if RISC-V has been tested with the out of order CPU at all! > I'm happy that at least it doesn't completely fail! > > For you problem of only fetching 1 instruction per cycle... I think it's > going to take some digging. My first guess would be that it could be a > problem with the advancePC() function that's implemented in the RISC-V > decoder (in gem5/arch/riscv), but I don't really have any specific reason > to think that :). > > You could try turning on some debug flags for the O3 CPU. Specifically, > Fetch might be helpful. > > Cheers, > Jason > > On Thu, May 24, 2018 at 4:06 PM Marcelo Brandalero < > mbrandal...@inf.ufrgs.br> wrote: > >> Hi all, >> >> I recently switched from gem5/x86 to gem5/RISCV due to some advantages of >> this ISA. >> >> I'm getting some weird simulation results and I realized my compiler was >> generating instructions for the compressed RISCV ISA extension (chp 12 >> in the user level ISA specification <https://riscv.org/specifications/>). >> The weirdness disappears when I use *--march* to remove these extensions. >> >> *So the question is: does gem5/RISCV support this ISA extension? *If so, >> I can share the weird results (maybe I'm missing something) but basically a >> wide-issue O3 processor fetches only max 1 instruction/cycle when it should >> probably be fetching more. >> >> If it doesn't support then it's all OK, I just find it a bit weird that >> the program executes normally with no warnings whatsoever. >> >> Best regards, >> >> -- >> Marcelo Brandalero >> PhD Candidate >> Programa de Pós Graduação em Computação >> Universidade Federal do Rio Grande do Sul >> _______________________________________________ >> gem5-users mailing list >> email@example.com >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > >
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