Hello,
I am trying to have a monitor between the CPU and L1 Cache, so for
src/cpu/BaseCPU.py, I edited the function "addPrivateSplitL1Caches":
...
#self.dcache_port = dc.cpu_side
self.monitor = CommMonitor()
self.monitor.trace = MemTraceProbe(trace_file="trace.txt")
self.dcache_port = self.monitor.slave
self.monitor.master = dc.cpu_side
..
I got an error: 'MemTraceProbe' is not defined
Then, I imported CommMonitor and MemTraceProbe in BaseCPU.py
However, MemTraceProbe cannot be imported successfully.
How to solve this problem?
I will appreciate any help.
Best regards,
Rosen
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