Sorry that I couldn't share the setup due to the complexity involved in sharing it. I am still working on it. Meanwhile, I tried running the same program on TimingSimpleCPU with BaremetalRISCV. It worked. So it looks like the error is with my CPU model. Sorry for posting a question without double-checking it.
On Fri, Jun 5, 2020 at 8:57 PM Jason Lowe-Power <[email protected]> wrote: > Hi Anuj, > > Does this result in incorrect execution? Could you give us a full example > of where this happens so we can reproduce it? > > Thanks, > Jason > > On Fri, Jun 5, 2020 at 8:07 AM Anuj Falcon via gem5-users < > [email protected]> wrote: > >> In RISCV, when the condition of the conditional compressed branching >> instruction is false, it's incrementing the PC value by 4 rather than 2. >> Has anyone faced this issue with RISCV ISA? If yes, how to go about it? >> >> -- >> >> --------------------------------------------------------------------------------- >> J ANUJ >> >> --------------------------------------------------------------------------------- >> _______________________________________________ >> gem5-users mailing list -- [email protected] >> To unsubscribe send an email to [email protected] >> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > > -- --------------------------------------------------------------------------------- J ANUJ ---------------------------------------------------------------------------------
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