Hello and thank you for your answer,
Yes I write assemply language to instantiate the counters. I don't bother with
perf even if I tried to access the cycle counter but the file descriptor didnt
open.
static int perf_fd_cpu_cycles;
static struct perf_event_attr attr_cpu_cycles;
attr_cpu_cycles.size = sizeof(attr_cpu_cycles);
attr_cpu_cycles.exclude_kernel = 1;
attr_cpu_cycles.exclude_hv = 1;
attr_cpu_cycles.exclude_callchain_kernel = 1;
attr_cpu_cycles.type = PERF_TYPE_RAW;
attr_cpu_cycles.config = 0x11;
/* Open the file descriptor corresponding to this counter. The counter
should start at this moment. */
if ((perf_fd_cpu_cycles = syscall(__NR_perf_event_open, &attr_cpu_cycles, 0,
-1, -1, 0)) == -1)
fprintf(stderr, "perf_event_open fail %d %d: %s\n", perf_fd_cpu_cycles,
errno, strerror(errno));
The above code is an example I used from the posts I attached but with the
cycle counter.
The assemply I use to instantiate the ccnt is the one provided in the libraries
Armageddon/libflush. I will take a look in the one you attach me.
As it seems all the event counters are different with the ones in the stats.txt.
But what I do is
M5 restestats
Run code (instantiate pmus -----> code --------> read pmus)
M5 dumpstats
So in a way I see why there is a difference. I plan to include the asm_volatile
of these instructions in my C code and see again.
Also for the probe points I can search it a little bit.
Regards
Nikos
-----Original Message-----
From: Giacomo Travaglini via gem5-users <[email protected]>
Sent: Thursday, November 19, 2020 11:09 AM
To: gem5 users mailing list <[email protected]>
Cc: Giacomo Travaglini <[email protected]>
Subject: [gem5-users] Re: Using perf_event with the ARM PMU inside gem5 on Linux
Hi Nikolaos
> -----Original Message-----
> From: POLYCHRONOU Nikolaos via gem5-users <[email protected]>
> Sent: 18 November 2020 07:20
> To: [email protected]
> Cc: POLYCHRONOU Nikolaos <[email protected]>
> Subject: [gem5-users] Re: Using perf_event with the ARM PMU inside
> gem5 on Linux
>
> Helllo.
>
> I encounter the following problem when I try to simulate the
> starter_fs.py in aarch64.
>
> Following these following posts https://www.mail-archive.com/gem5-
> [email protected]/msg18401.html <https://www.mail-archive.com/gem5-
> [email protected]/msg18401.html> &
> https://stackoverflow.com/questions/63988672/using-perf-event-with-the
> -
> arm-pmu-inside-gem5
> <https://stackoverflow.com/questions/63988672/using-
> perf-event-with-the-arm-pmu-inside-gem5>
>
> I did the steps to apply the patch and changes and also instantiate
> the pmus. I write a script in the image to access directly the registers.
>
That's great, I can see Pierre documented really well his work. Which branch
are you using?
Just so you know, all required patches are now merged into develop and will be
part of next Release (gem5v21).
When you say you are accessing the registers directly, do you mean you are
adding some inline Assembly to manually initialize the PMU? Or are you relying
on the perf_events APIs (which is basically a syscall)?
> I manage to read all the events except the cycle counter which always return
> 0.
> I try to read the cycle counter by instantiating a pmu event counter
> with 0x11 but as reading from the ccnt it didn't work as well.
>
If you are manually accessing the PMU via inline assembly (MSR/MRS), it might
be that you are not correctly initializing The cycle counter.
The following article explains how to access/initialize the PMU either manually
or via perf_event_open
http://zhiyisun.github.io/2016/03/02/How-to-Use-Performance-Monitor-Unit-(PMU)-of-64-bit-ARMv8-A-in-Linux.html
You can debug what is going on by
- Checking gem5 warnings in stdout/stderr
- Using the PMUVerbose debug flag
- Using gdb and put a breakpoint on any PMU read/write to understand what is
going on.
> How GEM5 increments this counter. Are the steps to read it the same as
> in a real platform or the simulator has a mismatch configuration?
>
> Also the values obtained reading the counters are not exactly the same
> as the
> m5 resetstats - m5 dumpstats. I guess maybe these two are syscalls as I read .
>
Which stats / event counters are different?
> Another question is how to add the other events that are not
> implemented. I tried to do the following in the ArmPMU.py but it
> didn't work despite seeing the events created in the console they return 0
> values.
>
> self.addEvent(ProbeEvent(self,0x01,icache,"L1I_CACHE_REFILL"))
>
>
>
> self.addEvent(ProbeEvent(self,0x0D, bpred, "BR_IMMED_RETIRED"))
>
>
>
> Probably you need to add some counters in the component? Or are the
> implemented and I do sth wrong?
>
>
Have you defined a probe point in the icache/bpred?
You should instantiate a pmuProbePoint in those classes; those will
automatically notify the PMU probe listener if wired correctly.
>
> Really want some guidance.
>
> Thank you
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> Nikolaos Foivos POLYCHRONOU
>
> PhD Student - Security of Embedded Systems/IoT/IIoT
>
> Département DSYS / LSOSP
>
>
>
> 17, rue des martyrs | 38000 Grenoble
>
> Fix work . +33 4 38 78 19 58
>
> Office Bat. 4022 - P. 221
>
> [email protected]
>
>
>
> LETI, technology research institute
>
> Commissariat à l'énergie atomique et aux énergies alternatives
>
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> Institutes
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> <https://www.youtube.com/channel/UC3JgudJblGykrECv6OUhWFg>
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