For the dtb i use the following armv8_gem5_v1_1cpu.dtb
Fot the configs/example/arm/devices.py? i do the following modifications:
def addPMUs(self, ints, events=[]):
"""
Instantiates 1 ArmPMU per PE. The method is accepting a list of
interrupt numbers (ints) used by the PMU and a list of events to
register in it.
:param ints: List of interrupt numbers. The code will iterate over
the cpu list in order and will assign to every cpu in the cluster
a PMU with the matching interrupt.
:type ints: List[int]
:param events: Additional events to be measured by the PMUs
:type events: List[Union[ProbeEvent, SoftwareIncrement]]
"""
assert len(ints) == len(self.cpus)
for cpu, pint in zip(self.cpus, ints):
int_cls = ArmPPI if pint < 32 else ArmSPI
for isa in cpu.isa:
isa.pmu = ArmPMU(interrupt=int_cls(num=pint))
isa.pmu.addArchEvents(cpu=cpu, itb=cpu.itb, dtb=cpu.dtb,
icache=getattr(cpu, 'icache', None),
dcache=getattr(cpu, 'dcache', None),
l2cache=getattr(self, 'l2', None))
for ev in events:
isa.pmu.addEvent(ev)
and in the
def SImpleSystem
def AddCaches
+ ints = [20 for i in range (self._num_cpus)]
# connect each cluster to the memory hierarchy
for cluster in self._clusters:
cluster.addPMUs(ints)
cluster.connectMemSide(cluster_mem_bus)
I am not sure this is the correct way to instantiate the pmu in the devices.py
but is seems to be working for what i want to do------ READ the registers with
assemply
Can you suggest me anothe rmore clever way if you have one?
Also when i load the module to enable user el0 access to the pmu it seems the
module is not working so yes maybe it sisnt recognized.
The PMU is enabled in the kernel config. i check this so many times but i am
not able to see the message in the boot that they are enabled as i saw in some
posts.
Verified again now. PMU is instantiated in the kernel config
________________________________________
From: Giacomo Travaglini [[email protected]]
Sent: 19 November 2020 11:41
To: POLYCHRONOU Nikolaos; gem5 users mailing list
Subject: RE: [gem5-users] Re: Using perf_event with the ARM PMU inside gem5 on
Linux
> -----Original Message-----
> From: POLYCHRONOU Nikolaos <[email protected]>
> Sent: 19 November 2020 10:25
> To: gem5 users mailing list <[email protected]>
> Cc: Giacomo Travaglini <[email protected]>
> Subject: RE: [gem5-users] Re: Using perf_event with the ARM PMU inside gem5
> on Linux
>
> Hello and thank you for your answer,
> Yes I write assemply language to instantiate the counters. I don't bother with
> perf even if I tried to access the cycle counter but the file descriptor didnt
> open.
> static int perf_fd_cpu_cycles;
> static struct perf_event_attr attr_cpu_cycles;
> attr_cpu_cycles.size = sizeof(attr_cpu_cycles);
> attr_cpu_cycles.exclude_kernel = 1;
> attr_cpu_cycles.exclude_hv = 1;
> attr_cpu_cycles.exclude_callchain_kernel = 1;
> attr_cpu_cycles.type = PERF_TYPE_RAW;
> attr_cpu_cycles.config = 0x11;
>
> /* Open the file descriptor corresponding to this counter. The counter
> should start at this moment. */
> if ((perf_fd_cpu_cycles = syscall(__NR_perf_event_open, &attr_cpu_cycles, 0,
> -1, -1, 0)) == -1)
> fprintf(stderr, "perf_event_open fail %d %d: %s\n",
> perf_fd_cpu_cycles, errno, strerror(errno)); The above code is an example I
> used from the posts I attached but with the cycle counter.
>
If you cannot open the file descriptor it means there is something wrong. It
means the Linux Kernel doesn't recognise a PMU.
This could be caused by one of the following reasons
1) You are not instantiating a PMU in the gem5 platform. Are you using the
addPMUs helper in configs/example/arm/devices.py?
2) Which DTB are you using? Are you relying on a prebuilt DTB or on
autogeneration? You should check if your DTB contains a valid PMU entry
3) Is the PMU driver enabled by your kernel configs?
https://community.arm.com/developer/ip-products/system/b/embedded-blog/posts/using-the-arm-performance-monitor-unit-pmu-linux-driver
>
> The assemply I use to instantiate the ccnt is the one provided in the
> libraries
> Armageddon/libflush. I will take a look in the one you attach me.
>
> As it seems all the event counters are different with the ones in the
> stats.txt.
> But what I do is
> M5 restestats
> Run code (instantiate pmus -----> code --------> read pmus)
> M5 dumpstats
I understand, but which events in particular? Anyway as it seems like the PMU
is not correctly configured, I would defer
The handling of this problem until we are sure we are doing things right.
Anyway I can tell you should expect a small mismatch:
M5 restestats <- gem5 starts counting here
Run code (instantiate pmus -----> code --------> read pmus) <- PMU starts
counting here
M5 dumpstats
>
> So in a way I see why there is a difference. I plan to include the
> asm_volatile of
> these instructions in my C code and see again.
>
> Also for the probe points I can search it a little bit.
> Regards
> Nikos
>
>
> -----Original Message-----
> From: Giacomo Travaglini via gem5-users <[email protected]>
> Sent: Thursday, November 19, 2020 11:09 AM
> To: gem5 users mailing list <[email protected]>
> Cc: Giacomo Travaglini <[email protected]>
> Subject: [gem5-users] Re: Using perf_event with the ARM PMU inside gem5 on
> Linux
>
> Hi Nikolaos
>
> > -----Original Message-----
> > From: POLYCHRONOU Nikolaos via gem5-users <[email protected]>
> > Sent: 18 November 2020 07:20
> > To: [email protected]
> > Cc: POLYCHRONOU Nikolaos <[email protected]>
> > Subject: [gem5-users] Re: Using perf_event with the ARM PMU inside
> > gem5 on Linux
> >
> > Helllo.
> >
> > I encounter the following problem when I try to simulate the
> > starter_fs.py in aarch64.
> >
> > Following these following posts https://www.mail-archive.com/gem5-
> > [email protected]/msg18401.html <https://www.mail-archive.com/gem5-
> > [email protected]/msg18401.html> &
> > https://stackoverflow.com/questions/63988672/using-perf-event-with-the
> > -
> > arm-pmu-inside-gem5
> > <https://stackoverflow.com/questions/63988672/using-
> > perf-event-with-the-arm-pmu-inside-gem5>
> >
> > I did the steps to apply the patch and changes and also instantiate
> > the pmus. I write a script in the image to access directly the registers.
> >
> That's great, I can see Pierre documented really well his work. Which branch
> are you using?
> Just so you know, all required patches are now merged into develop and will
> be part of next Release (gem5v21).
>
> When you say you are accessing the registers directly, do you mean you are
> adding some inline Assembly to manually initialize the PMU? Or are you relying
> on the perf_events APIs (which is basically a syscall)?
>
> > I manage to read all the events except the cycle counter which always return
> 0.
> > I try to read the cycle counter by instantiating a pmu event counter
> > with 0x11 but as reading from the ccnt it didn't work as well.
> >
>
> If you are manually accessing the PMU via inline assembly (MSR/MRS), it might
> be that you are not correctly initializing The cycle counter.
>
> The following article explains how to access/initialize the PMU either
> manually
> or via perf_event_open
>
> http://zhiyisun.github.io/2016/03/02/How-to-Use-Performance-Monitor-Unit-
> (PMU)-of-64-bit-ARMv8-A-in-Linux.html
>
> You can debug what is going on by
>
> - Checking gem5 warnings in stdout/stderr
> - Using the PMUVerbose debug flag
> - Using gdb and put a breakpoint on any PMU read/write to understand what is
> going on.
>
> > How GEM5 increments this counter. Are the steps to read it the same as
> > in a real platform or the simulator has a mismatch configuration?
> >
> > Also the values obtained reading the counters are not exactly the same
> > as the
> > m5 resetstats - m5 dumpstats. I guess maybe these two are syscalls as I
> > read .
> >
>
> Which stats / event counters are different?
>
> > Another question is how to add the other events that are not
> > implemented. I tried to do the following in the ArmPMU.py but it
> > didn't work despite seeing the events created in the console they return 0
> values.
> >
> > self.addEvent(ProbeEvent(self,0x01,icache,"L1I_CACHE_REFILL"))
> >
> >
> >
> > self.addEvent(ProbeEvent(self,0x0D, bpred, "BR_IMMED_RETIRED"))
> >
> >
> >
> > Probably you need to add some counters in the component? Or are the
> > implemented and I do sth wrong?
> >
> >
>
> Have you defined a probe point in the icache/bpred?
> You should instantiate a pmuProbePoint in those classes; those will
> automatically notify the PMU probe listener if wired correctly.
>
> >
> > Really want some guidance.
> >
> > Thank you
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > Nikolaos Foivos POLYCHRONOU
> >
> > PhD Student - Security of Embedded Systems/IoT/IIoT
> >
> > Département DSYS / LSOSP
> >
> >
> >
> > 17, rue des martyrs | 38000 Grenoble
> >
> > Fix work . +33 4 38 78 19 58
> >
> > Office Bat. 4022 - P. 221
> >
> > [email protected]
> >
> >
> >
> > LETI, technology research institute
> >
> > Commissariat à l'énergie atomique et aux énergies alternatives
> >
> > www.leti.fr <http://www.leti.fr/> | LETI is a member of the Carnot
> Institutes
> > network
> >
> >
> >
> >
> >
> >
> >
> > <https://www.youtube.com/channel/UC3JgudJblGykrECv6OUhWFg>
> > <https://twitter.com/cea_leti> <https://www.linkedin.com/company/leti>
> >
> >
> >
> >
> >
> >
>
> IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient,
> please notify the sender immediately and do not disclose the contents to any
> other person, use it for any purpose, or store or copy the information in any
> medium. Thank you.
> _______________________________________________
> gem5-users mailing list -- [email protected] To unsubscribe send an email
> to gem5-users-
> [email protected] %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient,
please notify the sender immediately and do not disclose the contents to any
other person, use it for any purpose, or store or copy the information in any
medium. Thank you.
_______________________________________________
gem5-users mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
