Hi Jonathan,

You can put the bridge wherever you would like. For MMIO things, you can
put it after the point of coherence, which is where we usually put the "I/O
crossbar."

You can poke around in configs/examples and util/systemc for some examples.

Cheers,
Jason

On Wed, Apr 26, 2023 at 4:30 PM Jonathan Kang <mos...@meta.com> wrote:

> Thanks!
>
>
>
> Would you have an example of how to instantiate this bridge? Also, I
> imagine this bridge is right after the CPU I and D side ports and before
> any membus that Gem5 has internally right?
>
>
>
> *From: *Jason Lowe-Power <ja...@lowepower.com>
> *Date: *Wednesday, April 26, 2023 at 4:27 PM
> *To: *The gem5 Users mailing list <gem5-users@gem5.org>
> *Cc: *Jonathan Kang <mos...@meta.com>
> *Subject: *Re: [gem5-users] Full System + external memory
>
> Hi Jonathan, Absolutely! You can set up a "bridge" which will take a
> subset of addresses and route to a different gem5 port. If you can convert
> from the port interface to the AXI, then it should "just work". Note that
> there
>
> Hi Jonathan,
>
>
>
> Absolutely! You can set up a "bridge" which will take a subset of
> addresses and route to a different gem5 port. If you can convert from the
> port interface to the AXI, then it should "just work". Note that there are
> also already bindings to SystemC/TLM in gem5 as well that could serve as
> good examples.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Wed, Apr 26, 2023 at 11:44 AM Jonathan Kang via gem5-users <
> gem5-users@gem5.org> wrote:
>
> I’m looking to integrate a Gem5 full system model with some of our
> internal IP. The IP and memory (caches) will be memory mapped. So I’d like
> it if the Gem5 full system could handle some parts of the system (file IO,
> system calls) but route requests to certain memory address regions to an
> external port (I’ve taken care of the conversion from Gem5 port to AXI
> SystemC). Is this possible?
>
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