Hello Clint, I am using the DRAMsim patch you sent a while ago and I am interested in see the contention of my workload. In your mail you say that using a bus will skew the results, can you or anyone please explain why a bus is going to cause this?. Also is there any alternative solution to see a more realistic contention.
Thanks a lot in advance. 2009/1/27 Clint Smullen <[email protected]>: > Ah, I see what you are saying, but that functionality actually resides > within DRAMsim itself. The doTiming method of the DRAMsim M5 object can take > as many packets as the network can give it, but it simply finds a free slot > in the BIU and places it there for DRAMsim to process on the next memory > controller cycle. On line 240, you will see the priority variable which is > constantly set to zero. According to the DRAMsim code, that is intended for > a purpose such as you are looking for, but I don't believe it does the > correct thing right now. If you have the priority field set based on the > core number, and then you modify/create a policy to do as you want within > DRAMsim, you should be able to get the desired behavior. > The biggest issue you may face is the fact that to actually make the system > work, you would have to have requests arrive at (nearly) the same time. If > the memory controller is connected to a bus, this is not possible, which > would skew the results. If the pressure on the memory system is high enough, > then it would be possible to see the selection policy in action, but it is > more difficult to guarantee. > Hopefully this information helps. > - Clint > > On Jan 27, 2009, at 11:52 AM, Angela Carlsson wrote: > > Hello Clint thanks a lot for the patch. I have been testing it and it seems > that works fine. Thanks a lot. > > I have a question regarding the reordering of the accesses. Do the selection > policies Greedy, FCFS... work?. What I mean is that when there are several > accesses at the *same* time all the accesses are stored inside of the > transaction queue in DRAMSim? or on the contrary the accesses are sent one > by one to DRAMSim (then DRAMSim process the petition and send the answer, in > this case DRAMSim works as FCFS). In this last case then they are stored in > the retry list in the bus.cc file. My interest for this is to give some > priorities for accesses from some cores, that's why I am asking this, > because I want to know who stores the petition, to reorder them there. > > I hope you knwo what I mean if not please let me know. Thanks a lot in > advance. > > >> Date: Fri, 23 Jan 2009 12:41:10 -0500 >> From: [email protected] >> To: [email protected] >> Subject: [m5-users] [PATCH] Beta patch for M5 2.0 DRAMsim implemention >> >> # HG changeset patch >> # User Clint Smullen <[email protected]> >> # Date 1232732406 18000 >> # Node ID a95dd3a28ecb82a074de030367fe641d52aaf148 >> # Parent 0397aa216e2290a50fb7138bd28563926573c929 >> Beta patch for M5 2.0 DRAMsim implemention. > > ________________________________ > Con el nuevo Windows Live lo tendrás todo al alcance de tu > mano _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
