On 05/05/2014 13:22, Matt Turner wrote: > On Mon, May 5, 2014 at 7:06 AM, Markos Chandras <[email protected]> wrote: >> Hi all, >> >> Right now the number of stages for each endianness is 8: >> >> - mips1 >> - mips32 >> - mips32r2 > > Do we need r1 and r2 stages? > > (Isn't r3 a thing now?)
I cannot speak for anything outside of the standard/original MIPS ISAs, but I thought we killed off mips1 long ago. When did that come back? Almost anything out there should be able to handle mips2 at a bare minimum (only R2000 and R3000-based systems, like certain DECStations, would need mips1). mips2 is also the branch point for the mips32r* ISAs, so if any of the original, 32-bit ISAs should be kept, that would be mips2. mips1 can go. >> - mips3 >> - mips4 >> - mips4_r10 > > Big endian only. > Seconded. We still support SGI systems, which max out at the mips4 ISA. If we drop support for mips3, that will cut off any R4x00-based Indigo2 and Indy systems, but I believe those to be fairly rare anyways (and the R4600 still has quirks about it that can pose challenges). mips4 little-endian is only useful for the old Cobalt RaQ2 and Qube hardware, which I don't think is reasonable anymore. Modern gcc takes long enough on an SGI system with a secondary cache -- the Cobalt's low-powered RM5231 with no L2 would make 4.8 or 4.9 even more excruciating. Max memory there is 256MB of RAM, and I don't know if gcc-4.9 will build under that. And I don't see a point in doing an R10K-specific mips4 build. The standard mips4 build is good enough, and users of R10K systems can rebuild to gain the R10K enhancements if needed. So, keep mips4 big-endian as a standard stage build, let's do a mips3 big-endian build maybe once or twice a year, and drop mips4 little-endian and R10K mips4. -- Joshua Kinard Gentoo/MIPS [email protected] 4096R/D25D95E3 2011-03-28 "The past tempts us, the present confuses us, the future frightens us. And our lives slip away, moment by moment, lost in that vast, terrible in-between." --Emperor Turhan, Centauri Republic
