Hi Tristan,
Thanks for the replay.
It seems that when I run my design with the "--disp-tree" option it still does not print anything. When I run some component of the design, lower in the hierarchy, with the display tree option it does print the hierarchy correctly.
It seems that the test bench did not connect the DUT correctly or something. I tried to search for any errors in the test bench or even case miss match (although if I remember correctly VHDL is case sensitive) but to no avail.
As I mentioned in my previous email, this design was tested using at-least one other simulator with no problems in this area.
Thanks,
Moti
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