Hi Tristan,
Did you get the design files of my project?
Moti
On 9/26/06, Tristan Gingold <[EMAIL PROTECTED]> wrote:
On Tue, Sep 26, 2006 at 12:16:10AM +0200, Moti Litochevski wrote:
> Hi Tristan,
>
> Thanks for the replay.
> It seems that when I run my design with the "--disp-tree" option it still
> does not print anything. When I run some component of the design, lower in
> the hierarchy, with the display tree option it does print the hierarchy
> correctly.
Humm this is strange.
Looks like a crash during elaboration.
> It seems that the test bench did not connect the DUT correctly or something.
> I tried to search for any errors in the test bench or even case miss match
> (although if I remember correctly VHDL is case sensitive) but to no avail.
--disp-tree should at least disp the top level entity. If nothing is
displayed, this is a bug.
> As I mentioned in my previous email, this design was tested using at-least
> one other simulator with no problems in this area.
Seems you hit a bug.
I am interesting by the commands you are using to run the simulation.
Can you send your design to me (privatly) ?
Can you try to narrow the bug ?
Tristan.
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