I get the error message: "../vhdl_source/test_generic.vhd:22:26: universal
integer bound must be numeric literal or attribute", when trying to compile
the following code.
---------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_generic is
generic (
width: natural;
awidth: natural
);
port(
clk: in std_logic;
reset: in std_logic;
we: in std_logic;
din: in std_logic_vector(width-1 downto 0);
dout: out std_logic_vector(width-1 downto 0);
addr: in std_logic_vector(awidth-1 downto 0)
);
end;
architecture test of test_generic is
type mem_type is array(0 to 2**awidth-1) of std_logic_vector(width-1 downto 0);
signal memory: mem_type;
begin
process(clk)
begin
if rising_edge(clk) then
if we='1' then
memory(to_integer(unsigned(addr)))<=din;
end if;
dout<=memory(to_integer(unsigned(addr)));
end if;
end process;
end;
---------------
I can get this construction to work if I add a constant with a value of
2**awidth-1. Unfortunately this construction is in the altera_mf library
which I would prefer not to change.
regards,
Mark van Doesburg
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