Hi, I'm new to GHDL, and VHDL in general, and I've run into a bit of a problem. I've written a small 1-bit comparator, that, with 1 and 1 as input, outputs 0 when compiled with GHDL. I've run a simulation in ModelSim, which produces the correct input, and the sourcecode is from a textbook, so that should be correct as well.
I've simulated using the tutorial at http://mbmn.net/uer/tutorials/vhdl-with-ghdl/. I've also tried using the -a and -e commands instead of -i and -m, but with no luck. I'd really prefer using this workflow, instead of having to boot into Windows to use the Student Edition of ModelSim, so any help would be much appreciated. i've pasted the sourcecode for both the circuit and the testbench below. Thanks. --sourcecode start library ieee; use ieee.std_logic_1164.all; entity eq1 is port ( i0, i1 : in std_logic; eq : out std_logic ); end eq1; architecture sop_arch of eq1 is signal p0, p1 : std_logic; begin -- sum of two products eq <= p0 or p1; -- product terms p0 <= (not i0) and (not i1); p1 <= i0 and i1; end sop_arch; --sourcecode end --testbench start library ieee; use ieee.std_logic_1164.all; entity eq1_tb is end entity; architecture tb_arch of eq1_tb is signal test_in0, test_in1, test_out : std_logic; begin uut : entity work.eq1(sop_arch) port map (i0 => test_in0, i1 => test_in1, eq => test_out); process begin test_in0 <= '0'; test_in1 <= '0'; wait for 20 ns; test_in0 <= '1'; test_in1 <= '0'; wait for 20 ns; test_in0 <= '0'; test_in1 <= '1'; wait for 20 ns; test_in0 <= '1'; test_in1 <= '1'; wait for 20 ns; end process; end architecture; --testbench end -- Venlig hilsen -Jens Henrik Skuldbøl _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
