On Thu, 17 Feb 2011 21:31:12 +0100, Jens Henrik Skuldbøl
<[email protected]> wrote:
Hi,
I'm new to GHDL, and VHDL in general, and I've run into a bit of a
problem.
I've written a small 1-bit comparator, that, with 1 and 1 as input,
outputs 0 when compiled with GHDL. I've run a simulation in ModelSim,
which produces the correct input, and the sourcecode is from a
textbook, so that should be correct as well.
I've simulated using the tutorial at
http://mbmn.net/uer/tutorials/vhdl-with-ghdl/. I've also tried using
the -a and -e commands instead of -i and -m, but with no luck.
I'd really prefer using this workflow, instead of having to boot into
Windows to use the Student Edition of ModelSim, so any help would be
much appreciated.
i've pasted the sourcecode for both the circuit and the testbench
below.
Thanks.
Hi,
the only disputable thing i see is the absence of output in the
testbench process.
GHDL will display nothing unless you ask it too.
use some "report" statements, like "report std_ulogic'image(eq);"
(check the syntax)
process
begin
test_in0 <= '0';
test_in1 <= '0';
wait for 20 ns;
eport std_ulogic'image(eq);
-- etc.
test_in0 <= '1';
test_in1 <= '0';
wait for 20 ns;
test_in0 <= '0';
test_in1 <= '1';
wait for 20 ns;
test_in0 <= '1';
test_in1 <= '1';
wait for 20 ns;
end process;
end architecture;
--testbench end
hope this helps :-)
YG
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