Hi *,
the Xilinx vivado tool chain creates simulation model where signal are
decorated with an 'attribute RTL_KEEP'. That can happen even for port
signals.
ghdl apparently does not allow that port signals are decorated and aborts
with an error
...:30690:25: no named entities '...' in declarative part
A reproducer is appended. Apparently ghdl considers only locally declared
signals, but not ports, in this case.
The syntax of attribute allows many entity_classes, one is 'signal', but
'port' isn't listed. My understanding is that port is, for these purposes,
simply a signal I see no reason why it can't be decorated with an attribute.
It be great if that would be corrected in a future release.
With best regards, Walter
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity bad_attribute is
port (
A : in std_logic;
B : in std_logic;
C : out std_logic
);
end bad_attribute;
architecture syn of bad_attribute is
attribute RTL_KEEP : string;
attribute RTL_KEEP of C : signal is "yes";
begin
C <= A and B;
end syn;
------------------------------------------
gives with ghdl 0.33
bad_attribute.vhd:23:25: no named entities 'c' in declarative part
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