On 12/06/16 15:26, Walter F.J. Mueller wrote:
Hi *,
the Xilinx vivado tool chain creates simulation model where signal are
decorated with an 'attribute RTL_KEEP'. That can happen even for port
signals.
ghdl apparently does not allow that port signals are decorated and aborts
with an error
...:30690:25: no named entities '...' in declarative part
A reproducer is appended. Apparently ghdl considers only locally declared
signals, but not ports, in this case.
The syntax of attribute allows many entity_classes, one is 'signal', but
'port' isn't listed. My understanding is that port is, for these purposes,
simply a signal I see no reason why it can't be decorated with an
attribute.
It be great if that would be corrected in a future release.
I am pretty sure that ghdl is correct here and Xilinx model is not.
But this could be relaxed with -frelax-rules
(Do not hesitate to open an issue on github).
Regards,
Tristan.
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