On 06/14/2016 12:57 AM, David Koontz wrote:
From IEEE Std 1076-1993, 5.1 Attribute specification, paragraph 9:
>...
Dear David, thanks for the in depth analysis !! I've posted it on the Xilinx forum, see https://forums.xilinx.com/t5/Simulation-and-Verification/wrong-attribute-decorations-of-port-signals-generated-by-write/m-p/704905#M16265 I haven't explicitly mentioned ghdl because Xilinx usually doesn't react when one goes beyond 'supported systems and tools'. When it runs with their own simulator and with ModelSim and a few other it's usually fine for them. But let's see what happens. Thanks again and with best regards, Walter P.S.: I have added a filter which removes attribute declarations. They don't affect simulation (at least in ghdl), that solves for me the immediate problem. _______________________________________________ Ghdl-discuss mailing list Ghdl-discuss@gna.org https://mail.gna.org/listinfo/ghdl-discuss
