On 04/15/2012 09:43 AM, Felix Salfelder wrote:
gnucap> spice
gnucap-spice>R1 1 2 3
gnucap-spice>.verilog
gnucap-verilog>list
resistor #(.r( 3.)) R1 (.p(1),.n(2));
now the geda plugin does what you intend, doesn't it?
What you say above is internal to gnucap. I'd like the existing
gnetlist output of a verilog-a netlist, (which is from a gnetlist back end
scheme plugin)
to work with gnucap, whether that means finding errors in the
verilog-a gnetlist back end, or in the gnucap verilog-a language plugin.
The motivation for above is that SPICE netlists don't hold as much info
compared to
verilog. I think adding some verilog
notation to gschem is possible and will allow better hierarchy use within
gschem.
As is, gschem can at best deal with flat named hierarchies. There is no
concept of
an instance number associated with any symbol. To have a buss of 3 wires
connect to
3 identical subschematics, you draw 3 differently refdes named symbols and
connect them.
The usual naming style is S1,S2,S3 for the identical sub schematics and a slash
separator:
So, R5 in the subschematic becomes S1/R5 and S2/R5 and S3/R5 in a flattened
netlist.
I'd like to keep that in mind as work is done on translators, hopefully making
future changes easier.
"if the verilog language plugin is incomplete (and i
guess it is), lets fix it! can you post an example?"
Not right now. It's been a year, and I have to work on my tax filing today and
tomorrow.
John
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