On Sunday 15 April 2012, al davis wrote: > RESISTOR R1 ( > .\2 ( unnamed_net1 ), > .\1 ( unnamed_net6 ) > ); > > The defects: > 1. No value for the resistor. > 2. Pin names are "\2" and "\1". They should be "p" and "n".
I forgot one: 3. RESISTOR is upper case. The one in the standard library is lower case. Verilog is case-sensitive. _______________________________________________ Gnucap-devel mailing list [email protected] https://lists.gnu.org/mailman/listinfo/gnucap-devel
