On 04/15/2012 04:12 PM, al davis wrote:
On Sunday 15 April 2012, John Griessen wrote:
> On 04/15/2012 01:28 PM,[email protected] wrote:
> > 2. Pin names are "\2" and "\1". They should be "p" and
> > "n".
>
> For many passive parts the symbol libraries are not
> polarized, so some kind of text processing of the netlist
> would be helpful, and it should be open and pointed out to
> the user so they aren't confused by its action. For a
> resistor or nonpolarized capacitor model, either way will be
> fine and better than doing nothing.
Regardless, there is a standard that should be followed. I
didn't create the standard. Admittedly, I am refering to the
Verilog-AMS standard, version 2.3, section E.4, page 367, table
E.1. This section defines interface to standard Spice
components. There may be others.
I'm looking at verilog and not sure which version we are talking about,
since the one you can download from accelera.org is jun 2009 v. 2.3.1,
and its table E.1 is on page 373 of a pdf named VAMS-LRM-2-3-1.pdf
I've started some wiki documentation for this at:
http://gnucap.org/dokuwiki/doku.php?id=gnucap:user:user
http://gnucap.org/dokuwiki/doku.php?id=gnucap:user:gnucap_verilog_reconciled
John
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