>
> For Harbour speedtst builds use -gc3 and -ko switches. -ko enables some
> optimizations which breaks some strict Clipper compatibility, f.e.
> different RT errors on wrong types in math operations but as I can see
> XPP does not respect Clipper compatibility in much more serious places
> so we should enable such optimizations also in Harbour.
I think we should enable -ko for Harbour builds. What do you think?
> Meanwhile I have a question about MSVC. The MSWIN documentation says
> that Interlocked*() functions should be inlined by compiler if possible.
> Viktor's ST and MT Harbour results suggests that MSVC does not make it.
Yes, indeed:
---
_hb_atomic_inc:
00000000: 8B 44 24 04 mov eax,dword ptr [esp+4]
00000004: 50 push eax
00000005: FF 15 00 00 00 00 call dword ptr
[__imp__interlockedincrem...@4]
0000000B: C3 ret
_hb_atomic_dec:
00000000: 8B 44 24 04 mov eax,dword ptr [esp+4]
00000004: 50 push eax
00000005: FF 15 00 00 00 00 call dword ptr
[__imp__interlockeddecrem...@4]
0000000B: F7 D8 neg eax
0000000D: 1B C0 sbb eax,eax
0000000F: 83 C0 01 add eax,1
00000012: C3 ret
---
> Can you try to make sth similar for MSVC?
> For hb_atomic_inc32 we need only:
> LOCK;
> INC p;
>
> and for hb_atomic_dec32:
> LOCK;
> DEC p;
> SETNE;
>
Maybe this code:
---
void hb_atomic_inc32( volatile int * p )
{
__asm
{
lock inc p
}
}
int hb_atomic_dec32( volatile int * p )
{
unsigned char c;
__asm
{
lock dec p
setne c
}
return c == 0;
}
---
Which results in this ASM:
---
_hb_atomic_inc32:
00000000: 55 push ebp
00000001: 8B EC mov ebp,esp
00000003: F0 FF 45 08 lock inc dword ptr [ebp+8]
00000007: 5D pop ebp
00000008: C3 ret
_hb_atomic_dec32:
00000010: 55 push ebp
00000011: 8B EC mov ebp,esp
00000013: 51 push ecx
00000014: F0 FF 4D 08 lock dec dword ptr [ebp+8]
00000018: 0F 95 45 FF setne byte ptr [ebp-1]
0000001C: 0F B6 45 FF movzx eax,byte ptr [ebp-1]
00000020: F7 D8 neg eax
00000022: 1B C0 sbb eax,eax
00000024: 83 C0 01 add eax,1
00000027: 8B E5 mov esp,ebp
00000029: 5D pop ebp
0000002A: C3 ret
---
Brgds,
Viktor
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