Werner Almesberger wrote:
Ian Stirling wrote:
I have a project based on ST micros cortex chips that bit-bangs SDRAM,
taking advantage of the block read function, and would in principle work
for keeping the LCD state when the CPU is off.
That's nice ... but, could we perhaps start with a problem statement
before the proposed solution ? I.e., what would this do that we want
to do but can't or can only do with undesirable consequences ?
Sorry.
I was unfortunately rushed at the time, and probably shouldn't have
posted without more thought.
The thought was that the chosen MPU might be able to fulfull multiple
roles - amongst them being able to run the LCD of the GTA03/... when
off, being able to be used as an SD expander, providing the emergency
recovery facility, ...
On reflection - this won't work so well as I understand it, as the RAM
is inside the SoC - and adding external lines from the SDRAM to the MPU
would cause probable congestion.
Also - I hadn't fully considered the number of lines - the design I was
using was an 8M*8 SDRAM paired to a 8 bit display, which is considerably
fewer (around 40) than the would be required by the 32M*32 (presumably)
of GTA03, and voltages will likely not be a match.
I still think it's worth a look if a SD expander is also needed, though
I have not actually used the SD/MMC functionality on these chips, or
looked at it in depth yet.
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