On Wed, Mar 30, 2022 at 10:12:10PM +0200, [email protected] wrote: > Seems "everything" is a module, and you can just call the top module > main if you'd like.
Not sure what you mean. What is a top module? There is only (exactly) one circuit in a gEDA schematic (didn't we agree to stick to this?). The standard suggests to call it "main", which is as close as you get to "objects at top-level". Now you may call it "fred", but that won't lead much further. Note how a "main" module provides a standard way to explicitly specify port names, port order and parameters -- and how useful this will be when interpreting hierarchical schematics with a different tool. > > >From there, you can think about flattening. Perhaps gnucap-geda does it > > "the wrong way", but it will adapt. > > >From what I read about verilog-ams, you don't need to flatten the nets, > it follows from the structure. Not sure what you mean. You can flatten the hierarchy, and there may be good reasons you would want that. How does this relate to Verilog-ams? It all depends on what you'd like to do. Please expand on that end. cheers felix
