Also posting to the devel list. This thread really should be there, because it is developer related.
On Thu, 31 Mar 2022 16:47:33 +0200 (CEST) [email protected] wrote: > > Not sure what you mean. What is a top module? > > https://www.accellera.org/images/downloads/standards/v-ams/VAMS-LRM-2-4.pdf > p.129 "6.1 Overview" > To describe a hierarchy of modules, the user provides textual definitions > of various modules. Each module definition stands alone; the definitions > are not nested. Statements within the module definitions create instances > of other modules, thus describing the hierarchy. > > p.131 "6.2.1 Top-level modules and $root" > Top-level modules are modules that are included in the source text, but do > not appear in any module instantiation statement, as described in 6.2.2. There's also, from IEEE Std 1364-2001, p. 165 =========================== 12. Hierarchical structures The Verilog HDL supports a hierarchical hardware description structure by allowing modules to be embedded within other modules. Higher-level modules create instances of lower-level modules and communicate with them through input, output, and bidirectional ports. These module input/output ports can be scalar or vector. As an example of a module hierarchy, consider a system consisting of printed circuit boards (PCBs). The system would be represented as the top-level module and would create instances of modules that represent the boards. The board modules would, in turn, create instances of modules that represent ICs, and the ICs could, in turn, create instances of modules such as flip-flops, mux s, and alu s. To describe a hierarchy of modules, the user provides textual definitions of the various modules. Each module definition stands alone; the definitions are not nested. Statements within the module definitions create instances of other modules, thus describing the hierarchy. ========================== A top-level model just sits there. It must be instantiated, but that is not your job. A generated file from a schematic is not expected to be all you need for simulation. It needs to be instantiated, and instruments need to be added. Gnucap has an extension to Verilog that lets you do this. Other simulators are all different in this regard. It is common to do the top level circuit in Spice mode. The name of a module corresponding to a schematic strictly doesn't matter, but you should give it a meaningful name, possibly user specified. If you don't have anything else and must pick a name automatically, the name of the file, with extensions stripped, would be a good choice. If the schematic is hierarchical, it may make sense to put them all on one file, each page as its own "module". If you want them as separate files, that's ok too. It's your choice.
