On Thu, Mar 31, 2022 at 04:47:33PM +0200, k...@aspodata.se wrote: > From what I understand after reading the above pdf, is that you can > flatten or not flatten. For a .sch to verilog-ams converter, I'd prefer > to keep the structure as it is in the .sch files, that would make it > easier to do backannotations.
Hi Karl. There might have been a misunderstanding. You write ".sch to verilog-ams converter", but then "the .sch files" (plural). Storing (NB: not converting) a gEDA schematic in verilog format does not require multiple .sch files. Do one at a time. The key is the explicit connectivity. Anything else follows, and will be more straightforward. Eventually, you could paste a bunch of modules into a single file, and rename them, if needed. > I'd use the sch file name without the .sch/.sym suffix as module name. This violates the "single point of truth" principle. Renaming a file will make the data inconsistent (but shouldn't). Renaming a .sch file has no such side-effect. cheers felix
