On Thu, 2010-07-29 at 03:38 -0700, FloofLeBo wrote:
> SRC_DIRS := Src0 Src1
> CPP_FILES := $(foreach SRC_DIR,$(SRC_DIRS),$(shell find $(SRC_DIR)
> -name "*.cpp"))
> And then a set of implicit rules generated by a foreach command:
>
> $(foreach, SRC_DIR,$(SRC_DIRS),\
> $(OBJDIR)/%.o : $(SRC_DIR)/%.cpp\
> ${Q}${CPP} -o $@ $^\
> )
>
> But this doesn't work (of course). Is there a way to do that easily
> (or not) in a makefile ?
You can use $(eval ...) for this (or, you could use auto-generated
included makefiles as well).
It can be a bit tricky to get the escaping right but it does work. For
example:
$(foreach SRC_DIR,$(SRC_DIRS), $(eval \
$(OBJDIR)/%.o : $(SRC_DIR)/%.cpp ; $${Q}$${CPP} -o $$@ $$^))
--
-------------------------------------------------------------------------------
Paul D. Smith <[email protected]> Find some GNU make tips at:
http://www.gnu.org http://make.mad-scientist.net
"Please remain calm...I may be mad, but I am a professional." --Mad Scientist
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