Yes, that's exactly what I want.
I've tried the solution using eval to produce one-line rules. Problem is,
they are on one line (which prevents having different prefixes
('@','-','!',...) on different commands in the recipe) . I found something
on gnu make manual (section 8.8) that should (but doesn't) work.
define OBJ_template =
$$(OBJDIR)/%.o: $(1)/%.cpp
@$$(MKDIR) -p $$(dir $$@)
echo "$$(BYELL)+dep+ $$(BBLUE)$...@$$(NOCOLOR)"
$$(CPP) $$(CCFLAGS) $$(INC) $$(DEFS) -o $$@ $$<
endef
$(foreach SRCDIR,$(SRCDIRS),$(eval $(call OBJ_template,$(SRCDIR))))
This leads to "no rule to make target <whatever>". I've tried the example
given in the make manual:
PROGRAMS = server client
server_OBJS = server.o server_priv.o server_access.o
server_LIBS = priv protocol
client_OBJS = client.o client_api.o client_mem.o
client_LIBS = protocol
# Everything after this is generic
.PHONY: all
all: $(PROGRAMS)
define PROGRAM_template =
$(1): $$($(1)_OBJS) $$($(1)_LIBS:%=-l%)
ALL_OBJS += $$($(1)_OBJS)
endef
$(foreach prog,$(PROGRAMS),$(eval $(call PROGRAM_template,$(prog))))
$(PROGRAMS):
@echo l $@ from $^
%.o:
@echo cc $@
clean:
@echo rm $(ALL_OBJS) $(PROGRAMS)
But this doesn't work either. It should output:
l server from server.o server_priv.o server_access.o
l client from client.o client_api.o client_mem.o
But instead I get:
l server from
l client from
Why is that happening ? I can't figure out I've also tried:
all: target1 target0
example = target0: $(1)
define exampleLine =
target1: $(1)
@echo $$@ depends on $$^
endef
$(eval $(call example,FooBar0))
$(eval $(call exampleLine,FooBar1))
target0:
@echo $@ depends on $^
target1:
@echo $@ depends on $^
which gives:
target1 depends on
cc FooBar0.o
cc FooBar0.o -o FooBar0
cc: FooBar0.o: No such file or directory
cc: no input files
make: *** [FooBar0] Error 1
I feel there seems to be a problem with multi-line variables, or with me ?
Which is which ?
Thanks,
Floof
On Fri, Jul 30, 2010 at 7:43 AM, Todd Showalter <[email protected]>wrote:
> On Thu, Jul 29, 2010 at 6:38 AM, FloofLeBo <[email protected]> wrote:
>
> > I am currently writing a Makefile which should work in several projects
> with
> > minimal edits.
> >
> > What I want is that within the Makefile of particular project we find:
> >
> >
> > SRC_DIRS := Src0 Src1
> > CPP_FILES := $(foreach SRC_DIR,$(SRC_DIRS),$(shell find $(SRC_DIR) -name
> > "*.cpp"))
> >
> >
> > And then a set of implicit rules generated by a foreach command:
> >
> >
> > $(foreach, SRC_DIR,$(SRC_DIRS),\
> > $(OBJDIR)/%.o : $(SRC_DIR)/%.cpp\
> > ${Q}${CPP} -o $@ $^\
> > )
>
> Are you sure that's what you want? It means that any code sitting
> in that directory is implicitly a live part of the project and
> therefore must compile and neither break nor conflict with anything.
> Personally, I've found it better to have (in each code directory) a
> file containing a list of the valid source files in that directory.
> You can then grab those and stitch them together into a master build
> list fairly easily.
>
> One advantage of the list is that it makes things play much more
> nicely with version control; the list can be version controlled too,
> and it means source files don't have to be moved around to change the
> active sources in the build. It's just a matter of commenting out the
> files you don't want in the list.
>
> For extra points, one can institute per-architecture lists to do
> platform-specific builds.
>
> Todd.
>
> --
> Todd Showalter, President,
> Electron Jump Games, Inc.
>
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