In a recent note, Randy Hudson said:
> Date: Thu, 13 Oct 2005 05:00:50 -0400
>
> The mod 30 used core memory. Because a memory read was destructive, the
> memory hardware would automatically rewrite data after reading it, raising a
> "busy" flag for the bank of ferrite cores including that bit until the
> rewrite was done. Memory was interleaved, so successive reads would come
> from different banks of core, usually avoiding having to wait on that busy
> flag. But the TRT instruction read the translate index, used it to fetch
> the translated value, then rewrote that value into the same byte from which
> the translate index had just been fetched, and therefore bumped into the
> busy flag. Of course, that rewrite was unnecessary in the TR case because
> the TR itself was about to write an updated value, but the memory hardware
> wasn't designed to accomodate that.
>
May I assume the same applied to NI and OI?
The PDP-6 (IIRC) had a read-pause-write mode of memory access in
which the rewrite was deferred until updated data was available,
thus performing such instructions in a single memory cycle.
More applicable to instructions such as NI and OI than to TR,
which requires an intervening memory access, of course.
And a colleague long ago described a system which had half-read
and half-write instructions, which would:
Fetch the storage content and leave the storage zeros.
Inclusive OR the register operand into the storage operand.
And nowadays, the behavior of dynamic RAM is quite the opposite:
it's necessary to periodically fetch each storage location; else
it forgets.
-- gil
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