re: http://www.garlic.com/~lynn/2011k.html#27 CLOCK change problem
32bit value with 15hr duration ... different models decrement bits depending on timer resolution of the model. re: http://www.bitsavers.org/pdf/ibm/360/funcChar/GA24-3231-7_360-30_funcChar.pdf pg. 29, Interval Timer The Model 30 Interval Timer (special feature) operates at a fixed cycle rate of 16.7 milliseconds (60-cycle system power-supply input) or 20 milliseconds (50-cycle power). The microprogram controls decrementing the timer The interval-timer microprogram requires 7.5 to 13.5 microseconds (10 to 18 microseconds in a CPU with 2-microsecond RW cycle) per count depending upon whether there is a carry in the count. The cycle occurs asynchronously with respect to the stored program and I/O operation. Backup-up register is provided with the timer feature to accumulate automatically a count of up to 16 intervals of time, if main storage cannot be accessed because of prolonged I/O or direct control operations. The feature permits a delay of up to 277 milliseconds between timer counter references without loss of the count. ... snip ... keeping 16 intervals ... implies that update has to happen before the end of 17th interval ... aka total 277ms divided by 17 intervals is approx. 16ms ... corresponds to the 16.7 milliseconds for 60-cycle power. re: http://www.bitsavers.org/pdf/ibm/360/funcChar/GA27-2719-2_360-67_funcChar.pdf pg. 19 High-Resolution Interval Timer An interval timer with a high degree of resolution is used in 2067. Operation of this timer is fully compatible with that described in the IBM System/360 Principles of Operation manual. The high-resolution timer provides approximately 13-usec resolution. This is accomplished with an 8-bit hardware register which contains the low-order byte of the timer. Each time the low-order byte counts to zero, the timer value at location 80-82 is decremented at the end of the instruction currently being executed. An operand fetch from location 80 will retrieve the three high-order bytes from location 80 plus the low-order bytes from the hardware register. If the low-order byte has stepped through zero during the instruction, then before a fetch from location 80, zeros are inserted into the low-order byte instead of the contents of the hardware register. Any instruction that stores into location 80 also stores the low-order byte into the hardware register, as well as a full word into location 80. If the timer value at location 80 changes from positive to negative, an external interrution is requested. ... snip ... approx. 15hr interval ... makes bit23 (i.e. bits 0-23) approx. 3mills. ... 360/67 timer required access to location 80 approx. every 3mills or machine would redlight. (bit31) 13microseconds *256 (bit23) is 3.328 milliseconds. 3.328 milliseconds times 2**24 is 15.51 hrs (for 32bits) bit23 at 3.328ms, bit22 at 6.656ms, bit21 at 13.312ms, bit20 at 26.624ms bit19 at 53.248ms, bit18 at 106.496ms, bit17 at 212.992ms misc. past posts mentioning doing clone controller http://www.garlic.com/~lynn/subtopic.html#360pcm -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
