=========================================
-----Original Message-----
From: "Walt Farrell" <[EMAIL PROTECTED]>
Sent: 7/27/2006 11:44 AM
To: "[email protected]" <[email protected]>
Subject: Re: Doing a LM of two words on a double word bounday - is it
serialized?
On 7/27/2006 11:54 AM, Jeffrey D. Smith wrote:
> The PoPs guarantees it. A "LM" for a double word-aligned
> operand will perform a concurrent 8-byte access. Same for STM.
>
> This is spelled out in the "Storage-Operand Consistency"
> specification in Chapter 5. Look at "Block-Concurrent References".
> ...snipped...
>
> LM R2,R3,operand ; no check-point synch, no store.
>
> will concurrently load R2,R3. The values are fetched 8-bytes
> in parallel. If another CPU is concurrently storing 8-bytes,
> then your CPU will see the entire old 8-bytes or the entire
> new 8-bytes and never a mixture of old and new bytes.
>
> Note that if another CPU is storing with a narrower alignment,
> like a 4-byte store, then you will get inconsistent results
> with either CDS or LM/STM.
That statement seems to contradict the "Block-Concurrent References"
section you referred to, so I'd like to understand your statement (or
the book) a little better.
From the book: "The instructions LOAD MULTIPLE, ... when the
operand or operands start on a word boundary, ...
access their storage operands in a left-to-right direction,
and all bytes accessed within each doubleword
appear to be accessed concurrently as observed by
other CPUs."
So, assuming an LM is of 2 words on a doubleword boundary it should not
matter whether another CPU is storing with narrower alignment. It could
matter if the LM was of 2 words on a word boundary, though. In that
case it could get 4 old bytes and 4 new bytes, I think. I think that
might be true even for another CPU storing 8 bytes not on a doubleword
boundary while LM loads 8 bytes not on a doubleword boundary.
Walt
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Just back-up a bit in the PoPs and read the "Block-Concurrent
References" paragraph. It all depends on the size of the block.
All CPU must be using the same block-size to ensure consistent
views. A full-word block is not the same as a double-word block.
The full-word store-type access is not necessarily "widened" to
a double-word access (or quad-word on Z machines). The CPU must
be using the same alignment and block width. The PoPs does not
say that different accesses to different block sizes is concurrent.
The full-word store is not a double-word concurrent store. Therefore
the double-word fetch is not protected from inconsistent results.
The block sizes are different. The specification only applies to
the same block access (alignment and width).
Jeffrey D. Smith
Farsight Systems Corporation
24 BURLINGTON DR
LONGMONT, CO 80501
303-774-9381 direct
303-709-8153 cell
303-484-6170 fax
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