On Thu, 31 May 2007 06:06:18 -0700 Edward Jaffe <[EMAIL PROTECTED]> wrote:
:>Binyamin Dissen wrote: :>> Usually instructions that cause stalls or delays are documented in the POPs. :>I wish that were true. Unfortunately, stalls and delays are almost never :>discussed in PoPs. For example, general purpose registers can be used :>for addressing. Therefore, every instruction that sets a general purpose :>register has the potential to stall/delay the pipeline due to Address :>Generation Interlock (AGI). There are special bypasses for LOAD and LOAD :>ADDRESS that reduce AGI. None of this is documented in PoPs. :>For more information, see the following SHARE presentation and the other :>articles and presentations to which its bibliography refers. :>http://shareew.prod.web.sba.com/client_files/callpapers/attach/SHARE_in_Baltimore/S8192DB073718.pdf Interesting reading. But I do understand the concept of address stalls. A SAM** should not require extra cycles and should not cause problems in the predictive execution. When you ran into delays, was it between 24 & 31 using BSM (which is not predictive) or was it with the SAM** instructions? -- Binyamin Dissen <[EMAIL PROTECTED]> http://www.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
