[EMAIL PROTECTED] (Rugen, Len) writes:
Virtual storage isn't exclusive to MVS - z/OS. One on of the best
presentations I recall was in a VM Performance and Tuning class.
Together with storage protection keys, page tables can be built to allow
different "users" to have various parts of private, shared for read and
shared for update storage. (At least update if you're friendly with the
think king and he lets you in key 0).
360/67 was machine that came with virtual memory as standard ... it
could be viewed somewhat as 360/65 with DAT box bolted on to the side
... although the 360/67 multiprocessor was significantly more sophisticated
that 360/65 multiprocessor (for instance, all 360/67 processors in a
multiprocessor complex could address all channels ... which wasn't true
of 360/65 multiprocessors) ... some multiprocessor digression from
a recent thread
http://www.garlic.com/~lynn/2007o.html#37 Each CPU usage
some of the people at the science center
http://www.garlic.com/~lynn/subtopic.html#545tech
were worried about some of the virtual memory issues ... some historical
comment that atlas virtual memory never worked well ... misc. past posts
mentioning atlas
http://www.garlic.com/~lynn/2000f.html#78 TSS ancient history, was X86 ultimate
CISC? designs)
http://www.garlic.com/~lynn/2001h.html#10 VM: checking some myths.
http://www.garlic.com/~lynn/2001h.html#26 TECO Critique
http://www.garlic.com/~lynn/2003b.html#1 Disk drives as commodities. Was Re:
Yamhill
http://www.garlic.com/~lynn/2003m.html#34 SR 15,15 was: IEFBR14 Problems
http://www.garlic.com/~lynn/2005o.html#4 Robert Creasy, RIP
http://www.garlic.com/~lynn/2006i.html#30 virtual memory
http://www.garlic.com/~lynn/2007e.html#1 Designing database tables for
performance?
http://www.garlic.com/~lynn/2007g.html#36 Wylbur and Paging
also reference to cp67 and vm370 historical paper
http://www.princeton.edu/~melinda/
anyway, as result of the concerns about virtual memory, cambridge
modified a 360/40 with custom virtual memory hardware ... prior to
360/67 availability. cp/40 virtual machine system was built for the
custom 360/40 ... which was remapped to cp/67 when 360/67 machines
became available.
virtual memory hardware support was eventually going to be made available
on 370s ... although only 24-bit virtual memory addressing ... 360/67
had support for both 24-bit virtual memory addressing as well as 32-bit
virtual memory addressing.
originally 370 virtual memory was going to have a lot more features.
the translation of the cp67 virtual machine system to vm370 virtual
machine system was going to include use of some of these additional
features. one specific feature that was going to be used was virtual
memory shared segment .... allowing the same shared segment to appear
in multiple different virtual address spaces ... and be read/only
protected.
retrofitting 370 virtual memory hardware support to 370/165 ran into
some schedule delays ... in order to make up those delays, lots of
370 virtual memory features were dropped ... and the other machines
that had implemented the full 370 virtual memory support had to
remove the additional features. in escalation meetings about
the trade-off delaying 370 virtual memory availability by
six more months (because of hardware implementation issues for
370/165) or shipping a subset six months earlier ... the favorite
son operating system took the position that they didn't need
any of the additional features.
this had a fairly big impact on vm370 implementation which including
coming up with a emulation of shared segment protection using a
kludge involving storage keys.
the initial translation of os/360 MVT to virtual memory environment
(for os/vs2 svs) involved creating a single 16mbyte virtual
address space and hacking a simple paging support into the side
of MVT. Then CCWTRANS (from cp67) was integrated into the MVT kernel
to provide for channel program translation (i.e. handle all
the stuff of taking the application space channel program that
had been created with virtual address ... creating a copy substituting
real addresses, pinning the associated pages, and all the
rest of the gorp).
misc. past posts mentioning the 370/165 virtual memory implementation
schedule problems and impact on vm370 implementation
http://www.garlic.com/~lynn/2000.html#59 Multithreading underlies new
development paradigm
http://www.garlic.com/~lynn/2003d.html#53 Reviving Multics
http://www.garlic.com/~lynn/2003f.html#14 Alpha performance, why?
http://www.garlic.com/~lynn/2004p.html#8 vm/370 smp support and shared segment
protection hack
http://www.garlic.com/~lynn/2004p.html#9 vm/370 smp support and shared segment
protection hack
http://www.garlic.com/~lynn/2004p.html#10 vm/370 smp support and shared segment
protection hack
http://www.garlic.com/~lynn/2004p.html#14 vm/370 smp support and shared segment
protection hack
http://www.garlic.com/~lynn/2005.html#3 [Lit.] Buffer overruns
http://www.garlic.com/~lynn/2005.html#5 [Lit.] Buffer overruns
http://www.garlic.com/~lynn/2005e.html#53 System/360; Hardwired vs. Microcoded
http://www.garlic.com/~lynn/2005f.html#45 Moving assembler programs above the
line
http://www.garlic.com/~lynn/2005f.html#46 Moving assembler programs above the
line
http://www.garlic.com/~lynn/2005h.html#10 Exceptions at basic block boundaries
http://www.garlic.com/~lynn/2005j.html#39 A second look at memory access
alignment
http://www.garlic.com/~lynn/2005j.html#54 Q ALLOC PAGE vs. CP Q ALLOC vs ESAMAP
http://www.garlic.com/~lynn/2005o.html#10 Virtual memory and memory protection
http://www.garlic.com/~lynn/2006.html#13 VM maclib reference
http://www.garlic.com/~lynn/2006b.html#39 another blast from the past
http://www.garlic.com/~lynn/2006i.html#9 Hadware Support for Protection Bits:
what does it really mean?
http://www.garlic.com/~lynn/2006i.html#23 Virtual memory implementation in S/370
http://www.garlic.com/~lynn/2006i.html#43 virtual memory
http://www.garlic.com/~lynn/2006j.html#5 virtual memory
http://www.garlic.com/~lynn/2006j.html#41 virtual memory
http://www.garlic.com/~lynn/2006l.html#22 Virtual Virtualizers
http://www.garlic.com/~lynn/2006m.html#26 Mainframe Limericks
http://www.garlic.com/~lynn/2006m.html#54 DCSS
http://www.garlic.com/~lynn/2006s.html#61 Is the teaching of non-reentrant
HLASM coding practices ever defensible?
http://www.garlic.com/~lynn/2006t.html#1 Is the teaching of non-reentrant HLASM
coding practices ever
http://www.garlic.com/~lynn/2006t.html#16 Is the teaching of non-reentrant
HLASM coding practices ever defensible?
http://www.garlic.com/~lynn/2006u.html#26 Assembler question
http://www.garlic.com/~lynn/2006u.html#60 Why these original FORTRAN quirks?
http://www.garlic.com/~lynn/2006w.html#7 Why these original FORTRAN quirks?
http://www.garlic.com/~lynn/2006w.html#11 long ago and far away, vm370 from
early/mid 70s
http://www.garlic.com/~lynn/2006w.html#23 Multiple mappings
http://www.garlic.com/~lynn/2006y.html#26 moving on
http://www.garlic.com/~lynn/2007d.html#32 Running OS/390 on z9 BC
http://www.garlic.com/~lynn/2007f.html#14 more shared segment archeology
http://www.garlic.com/~lynn/2007f.html#16 more shared segment archeology
http://www.garlic.com/~lynn/2007g.html#14 ISPF not productive
http://www.garlic.com/~lynn/2007j.html#43 z/VM usability
misc. past posts mentioning hacking cp67's CCWTRANS into the
side of MVT ... initial effort to migrate MVT to OS/VS2 SVS:
ttp://www.garlic.com/~lynn/2000c.html#34 What level of computer is needed for a
computer to Love?
http://www.garlic.com/~lynn/2001b.html#18 Linux IA-64 interrupts [was Re:
Itanium benchmarks ...]
http://www.garlic.com/~lynn/2001i.html#37 IBM OS Timeline?
http://www.garlic.com/~lynn/2001i.html#38 IBM OS Timeline?
http://www.garlic.com/~lynn/2002c.html#39 VAX, M68K complex instructions (was
Re: Did Intel Bite Off More Than It Can Chew?)
http://www.garlic.com/~lynn/2002n.html#62 PLX
http://www.garlic.com/~lynn/2003k.html#27 Microkernels are not "all or
nothing". Re: Multics Concepts For
http://www.garlic.com/~lynn/2004.html#18 virtual-machine theory
http://www.garlic.com/~lynn/2004e.html#40 Infiniband - practicalities for small
clusters
http://www.garlic.com/~lynn/2004o.html#57 Integer types for 128-bit addressing
http://www.garlic.com/~lynn/2005f.html#47 Moving assembler programs above the
line
http://www.garlic.com/~lynn/2005t.html#7 2nd level install - duplicate volsers
http://www.garlic.com/~lynn/2006.html#31 Is VIO mandatory?
http://www.garlic.com/~lynn/2006b.html#25 Multiple address spaces
http://www.garlic.com/~lynn/2006j.html#27 virtual memory
http://www.garlic.com/~lynn/2007f.html#6 IBM S/360 series operating systems
history
http://www.garlic.com/~lynn/2007f.html#33 Historical curiosity question
http://www.garlic.com/~lynn/2007n.html#35 IBM obsoleting mainframe hardware
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