On Tue, 22 Jan 2008 08:00:52 -0500, Peter Relson wrote:
>You can be certain that POST will always support the CS quick-post protocol
>and the LOCAL LOCK.
>
OK. I'll be confident. But why is this not documented in the
Assembler Services Reference? Interestingly, there, I see for POST:
#<<< 51.1.6 "z/OS V1R9.0 MVS Assembler Services Reference IAR-XCT"
__________________________________________________________________________________
51.1.6 Performance Implications
None.
I would consider it at least a performance implication that POST is
inferior to CS conditionally bypassing POST.
>-- Waiter wakes up, clears the ECB, then does its stuff (posssibly going
>back to wait). Waiter should not "do its stuff" and then "clear the ECB".
>
(I did say "clear the ECB" before POSTing the other task, didn't I?)
That's "should", not "must". And why not? It can't really matter,
because even if the code is the minimal:
WAIT
L R1,ECB Preserve condition code
XC ECB,ECB Clear ECB for next cycle
... there's still the possibility that the waiter will lose control
and some other task be dispatched between the WAIT and the XC. Is
there any hazard in another task's (or the same task's) being able
to observe the ECB with the POST bit set? If the concern is that
the path from WAIT to XC may be so long that the waiter misses a POST
by the other task during that interval, the design is wrong. The
coder mustn't (not "shouldn't") count on winning that race.
-- gil
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