The following message is a courtesy copy of an article
that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well.

[email protected] (Scott Rowe) writes:
> Well, I've never heard of a large PowerPC server, I think you are referring 
> to POWER.

re:
http://www.garlic.com/~lynn/2008r.html#71 Curiousity: largest parallel sysplex 
around?
http://www.garlic.com/~lynn/2008r.html#72 Curiousity: largest parallel sysplex 
around?

as mentioned here
http://www.garlic.com/~lynn/2008r.html#43 another one biting the dust?

power (rios) started out multi-chip, high-end processor that didn't have
any provisions for multiprocessor operation (no cache consistency
operation). paperweight image with (original) six chip rios/power
http://www.garlic.com/~lynn/riospw.jpg

power/pc was targeted for single-chip implementation that would have
(eventually) cache consistency support for smp, tightly-coupled,
shared-memory, multiprocessor operation.

this is item (referenced in the above) to converge the two

POWER4 System Microarchitecture
http://www-03.ibm.com/systems/p/hardware/whitepapers/power4.html

from above:

With POWER4, the convergence of iSeries and pSeries microprocessors will
reach a new level. POWER4 was designed from the outset to satisfy the
needs of both of these systems.

... snip ...

as referenced ... one of the reasons that we were doing cluster scale-up
in this period (jan92)
http://www.garlic.com/~lynn/95.html#13

was because there was no cache consistency support (original power ...
and multiprocessor power/pc didn't yet exist).

lots of past posts mentioning ha/cmp product
http://www.garlic.com/~lynn/subtopic.html#hacmp

and old email mention working on ha/cmp scaleup
http://www.garlic.com/~lynn/lhwemail.html#medusa

and there was nothing in medusa (architecture) that would preclude
having clusters (i.e. loosely-coupled) of tightly-coupled
multiprocessors.

-- 
40+yrs virtualization experience (since Jan68), online at home since Mar70

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