Hi all,
I'm looking at what I think is a timing related issue with a piece of
work that is running in another AS in XMS mode on z/OS 1.12.
In the dump I can see two STCK values taken about 100 assembler instructions
apart that show a time difference of over a second. I can't see anywhere in
the code path that we would spin or wait, So why the gap?
Looking at the MVS trace I see a couple of TIME-GAP entries for a total 14
seconds for one of the 4 CPUs in this LPAR.
The last thing before the first entry and the only thing before and after the
2nd TIME-GAP entries are EMS (emergency signal) entries followed by a PC to
"SysTrace Processor Snap " and a wait.
Now it could be that this CPU just has nothing to do but I'm not sure.
The registers in the TCB are old so I don't think we've been preempted by z/OS
on this LPAR and I was wondering if perhaps the Virtual CPU had been pulled
from under us by another LPAR and if that sort of interupt behaved differently
or just the same as any other?
My questions are
1) What are the signs of a CPU being preempted and given to another LPAR?
2) Presumably this can happen on any instruction boundary? If it happens where
do the registers get stored? Is it the same place as for a z/OS interupt, i.e.
in the TCB?
3) Does the preempted piece of work have to wait for that CPU to come back or
can it be dispatched on another CPU in the LPAR?
4) I get a dump via an IF slip on the instruction AFTER the STCK, i.e. we ended
up with PSW 2 instructions after STCK. would this impact the output from the
STCK?
Thanks in advance,
Ron.
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