On Thu, 15 Nov 2012 07:48:32 -0600, Ron MacRae wrote: >1) What are the signs of a CPU being preempted and given to another LPAR? >2) Presumably this can happen on any instruction boundary? If it happens >where do the registers get stored? Is it the same place as for a z/OS >interupt, >i.e. in the TCB?
AFAIK, PR/SM doesn't know or care about operating system structures. If it did, it would also have to know about VM, GNU/Linux and any other operating systems that could run in the LPAR. When the processor is assigned to another LPAR, PR/SM has to save the state of the processor in storage that PR/SM controls. Presumably, this would be in HSA. Also, if that information was stored in the memory that is assigned to the LPAR, it would be possible for another processor in the LPAR to modify that information, causing errors. >3) Does the preempted piece of work have to wait for that CPU to come back or > can it be dispatched on another CPU in the LPAR? It can be dispatched on another CPU. Hiperdispatch tries not to do that. >4) I get a dump via an IF slip on the instruction AFTER the STCK, i.e. we >ended up >with PSW 2 instructions after STCK. I think that is normal. >would this impact the output from the STCK? What do you mean by that? The STCK is finished. -- Tom Marchant ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
