"Low-address protection is under control of bit 35 of control register 0, the low-address-protection-control bit. When the bit is zero, low-address protection is off; when the bit is one, low-address protection is on."
Charles -----Original Message----- From: IBM Mainframe Discussion List [mailto:[email protected]] On Behalf Of Charles Mills Sent: Tuesday, February 22, 2022 10:20 AM To: [email protected] Subject: Re: 2.5 Heads Up Right ... Is there a control register bit or something like that for authority to store in the PSA (+ Key 0 of course). Charles -----Original Message----- From: IBM Mainframe Discussion List [mailto:[email protected]] On Behalf Of Lennie Dymoke-Bradshaw Sent: Tuesday, February 22, 2022 9:26 AM To: [email protected] Subject: Re: 2.5 Heads Up There will be multiple versions of that address for PSA for each active processor in the LPAR. I don't think that KEY 0 is adequate authority to store there either. Could be done from a hardware console though. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
