No, I'm claiming that LA R1,0(,R1) doesn't clear bits 0-31. Specifying base and 
index as 0 is a special case and clears all but the 12 bits of the displacement.

________________________________________
From: IBM Mainframe Discussion List <IBM-MAIN@LISTSERV.UA.EDU> on behalf of 
Paul Edwards <mutazi...@gmail.com>
Sent: Thursday, February 2, 2023 7:36 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: GETMAIN LOC=32

Are you claiming that:

LA R3,0

in AM64

does not clear bits 0-31?

What are you looking at in the POP (which I quoted)?

Are you able to run a test program that demonstrates that?

ie:

LG R3,=X'FFFFFFFFFFFFFFFF'
LGR R4,R3
LA R3,0

DC H'0'

and show me the registers?

I can't easily do that myself.

Thanks. Paul.




On Fri, 3 Feb 2023 00:30:11 +0000, Seymour J Metz <sme...@gmu.edu> wrote:

>Yes, I know that the wording is different depending on the mode. The point isd 
>that in no addressing mode does LA clear bits 0-31 to zero.
>
>
>--
>Shmuel (Seymour J.) Metz
>http://mason.gmu.edu/~smetz3
>
>________________________________________
>From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of 
>Paul Edwards [mutazi...@gmail.com]
>Sent: Thursday, February 2, 2023 7:26 PM
>To: IBM-MAIN@LISTSERV.UA.EDU
>Subject: Re: GETMAIN LOC=32
>
>Those words are not used for AM64.
>
>I am siscussing running 32-bit (L/LM/ST/etc) programs in AM64.
>
>BFN. Paul.
>
>
>
>
>On Fri, 3 Feb 2023 00:24:11 +0000S Seymour J Metz <sme...@gmu.edu> wrote:
>
>>"and bits 0-31 remain unchanged" does not mean set to zero.
>>
>>
>>--
>>Shmuel (Seymour J.) Metz
>>http://mason.gmu.edu/~smetz3
>>
>>________________________________________
>>From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of 
>>Paul Edwards [mutazi...@gmail.com]
>>Sent: Thursday, February 2, 2023 6:47 PM
>>To: IBM-MAIN@LISTSERV.UA.EDU
>>Subject: Re: GETMAIN LOC=32
>>
>>On Thu, 2 Feb 2023 23:37:16 +0000, Seymour J Metz <sme...@gmu.edu> wrote:
>>
>>>The semantics of LA are that it doesn't clear the top half in AM64.
>>
>>LOAD ADDRESS
>>
>>LA R�,D�(X�,B�) [RX]
>>
>>In the 24-bit addressing mode, the address is
>>placed in bit positions 40-63, bits 32-39 are set to
>>zeros, and bits 0-31 remain unchanged.. In the
>>31-bit addressing mode, the address is placed in
>>bit positions 33-63, bit 32 is set to zero, and bits
>>0-31 remain unchanged. In the 64-bit addressing
>>mode, the address is placed in bit positions 0-63.
>>
>>
>>Ergo, LA R3,0 in AM64 will set the entire 64 bits of R3 to 0.
>>
>>Which is all I need.
>>
>>And a S/370 instruction.
>>
>>> Even if you clear the top halves yourself, there are still coding
>>> issues for 31-bit addresses in AM64.
>>
>>Fix the coding issues so that they are AM32/64-clean?
>>
>>Also they aren't really 31-bit addresses. If an "L" instruction
>>is used to load an address, it is a 32-bit address, which will
>>suddenly be visible when running in AM64 (or a restored
>>360/67 running as AM32).
>>
>>BFN. Paul.
>>
>>
>>
>>>--
>>>Shmuel (Seymour J.) Metz
>>>http://mason.gmu.edu/~smetz3
>>>
>>>________________________________________
>>>From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of 
>>>Paul Edwards [mutazi...@gmail.com]
>>>Sent: Thursday, February 2, 2023 6:24 PM
>>>To: IBM-MAIN@LISTSERV.UA.EDU
>>>Subject: Re: GETMAIN LOC=32
>>>
>>>On Thu, 2 Feb 2023 23:22:00 +0000, Seymour J Metz <sme...@gmu.edu> wrote:
>>>
>>>>> And given that the high 32 bits are required to be 0, by convention,
>>>>
>>>>Where do you see that?
>>>
>>>That was my first message in the last 24 hours.
>>>
>>>Do an LA on program entry, for all undefined registers.
>>>
>>>Maybe I should have said "proposed convention". I'm happy
>>>to switch semantics to whatever is less confusing.
>>>
>>>BFN. Paul.
>>>
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