Thanks That’s what I thought In order for my recovery to do a retry My register have to be in tact
R3 is the base for all my csects 4 bytes off that is my eyecatcher as I branch round that comparing R3 + 4 for the eyecatcher is how I determine that I start SDWAGR then I try SDWASR Then I try the rbregs I preface everything with a TPROT If everything fails I percolate For 2 out 3 there 64 bit registers Thanks > On Apr 1, 2023, at 8:12 AM, Peter Relson <rel...@us.ibm.com> wrote: > > <snip> > Are the registers at SDWASR00 the same as the registers pointed to by > SDWARBAD when SDWARBAD is around I have noticed most of the time they are > </snip> > > Your words of "most of the time" indicate that you have observed that they > are not always. > Your observation is correct. Sometimes yes, sometimes no. Read the comment on > the field. > And the RB in which the error occurred is not necessarily the RB that created > the recovery routine. > > There is very limited diagnostic use of that data, so we did not feel it > necessary to spend storage space in the SDWA to provide the 64-bit high > halves or 16-byte psw. > > Peter > > > ---------------------------------------------------------------------- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
