You are doing a poor job of responding to questions and providing details.
When a program running in TCB mode is interrupted, the registers are stored in the TCB and the PSW is stored in the RB. If a new RB is created, for example because of SVC 13, the registers from the TCB are copied into the new RB. Chaining back from the abending RB (via RBLINK) will not provide useful information about the abend. Did you look in the next RB? -- Tom Marchant On Tue, 16 Jan 2024 09:43:16 -0500, Joseph Reichman wrote: >I was running under TESTAUTH > >I produced an abend in a space switching pc stacking routine > >SDWAEC2 matched up with the linkage stack PSW > >SDWAEC1 matched up with RBOPSW of SDWARBAD sdwagrsv didn’t match the rb regs >Chaining back RBLINK equal TCB so I was at the end of the RBs > >> On Jan 16, 2024, at 9:39 AM, Seymour J Metz <[email protected]> wrote: >> >> Was it SRB or TCB? Which RBs did you look at. >> >> Providing more details in your questions would enable better answers. If you >> have a situation where you're not allowed to post details, it's best to say >> so up front. >> >> -- >> Shmuel (Seymour J.) Metz >> http://mason.gmu.edu/~smetz3 >> עַם יִשְׂרָאֵל חַי >> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר >> >> ________________________________________ >> From: IBM Mainframe Discussion List <[email protected]> on behalf of >> Joseph Reichman <[email protected]> >> Sent: Tuesday, January 16, 2024 9:33 AM >> To: [email protected] >> Subject: Re: sdwagrsv not equal rbgrsave >> >> Seymour in my case sdawgrsv wasn’t in either TCB regs or rb regs >> >> Im sure Peter knows where they are located if they are in some internal IBM >> controls block ( in which case he can not or it would be useless to tell me) >> >> But I just don’t think that’s the case >> >>> On Jan 16, 2024, at 9:29 AM, Seymour J Metz <[email protected]> wrote: >>> >>> Logic does not dictate where to store registers; there are at least two >>> equally logical locations. In a z/OS TCB environment, the RB holds the >>> caller's registers and the TCB holds the current registers with a few >>> exceptions. This is documented. >>> >>> For SRB mode I'm not sure how much is GUPI. >>> >>> -- >>> Shmuel (Seymour J.) Metz >>> http://mason.gmu.edu/~smetz3 >>> עַם יִשְׂרָאֵל חַי >>> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר >>> >>> ________________________________________ >>> From: IBM Mainframe Discussion List <[email protected]> on behalf of >>> Joseph Reichman <[email protected]> >>> Sent: Tuesday, January 16, 2024 8:34 AM >>> To: [email protected] >>> Subject: Re: sdwagrsv not equal rbgrsave >>> >>> Peter >>> >>> Its my understanding that everything in the SDWA is copied from another >>> control block somewhere in the case of SDWAEC2 you helped me locate that in >>> the linkage stack. >>> >>> For SDWAEC1 I was able to locate that in the RBOPSW of SDWARBAD >>> >>> My logic tells me that PSW and REGS go together but when I tried to match >>> up SDWAGRSV to TBGRSAVE it didn’t. >>> >>> I think tried chaining back via RBLINK, but I got the TCB address meaning >>> it was the end of the chain. >>> >>> Grasping at straws I looked at TCBREGS, but it was there either. >>> >>> If the error regs SDWAGRSV are in some private IBM control block I can >>> understand that you cannot, or it would be useless to tell me. >>> >>> But my gut tells me it somewhere I can access it. >>> >>> >>> thanks >>> >>> -----Original Message----- >>> From: IBM Mainframe Discussion List <[email protected]> On Behalf Of >>> Peter Relson >>> Sent: Tuesday, January 16, 2024 5:09 AM >>> To: [email protected] >>> Subject: Re: sdwagrsv not equal rbgrsave >>> >>> Simple experimentation will show what you need to know about what is saved >>> where. >>> For example, suppose your mainline links to another routine.You mainline's >>> RB and the LINK target's RB can be examined. >>> Or suppose your mainline has an ESTAE and abends.You can examine the >>> mainline's RB, then the (next newer) RTM SVRB, then the (next newer) ESTAE >>> routine's PRB. >>> If you were trying to think about why it does what you will figure out that >>> it does, you'd realize that the regs that the SVC interrupt handler >>> processing wants to use have to be saved really quickly but the PSW is >>> already captured (in SVC Old PSW). >>> >>> Peter Relsonz/OS Core Technology Design ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
