Most of the key points have already been mentioned by others. Important thing to remember is that GHz on their own don't mean much.
A bit of history: zEC12 was 5.5 GHz, z13 went down to 5.0 GHz, z14 5.2 GHz, z15 5.2 GHz, z16 5.2 GHz, z17 5.5 GHZ At the time of the z13 announcement there was a lot discussion as to how going from 5.5 GHz to 5.0 GHz gave a better 'performance'. It has to do with the total System design and not just GHz. Below are some points which were made at that time and are still relevant etc. §Why the overall CPU frequency evolution approach is changing ? ̶Consistent frequency growth in the past decade •from hundreds of MHz to GHz ̶Core frequency has been reduced in the past couple of years̶ Designing chips for better performance ̶Limits are imposed by physics, technology or economics ̶Limitations in core frequency drives improvements in different dimensions ̶Different processor architectures have different issues with core frequency increase Physical limitations ̶Speed of signal lines form one end to the other on a chip ̶Power consumption and heat dissipation (cooling) ̶How many memory elements (caches) can be within a given latency from the CPU Physical limitations force the designers to make trade-offs ̶“Shrinking” a processor chip •pro: Faster due to shorter signal lines •con: Reduced area for heat dissipation ̶Lowering the processor voltages would make transistors switch quicker •pro: Frequency could then be increased •con: Current also increases creating more heat §Sounds easy.. but… it causes serious problems with cooling GHz is not the only dimension that matters ̶z Systems focus is on balanced system design across many factors: •Frequency, pipeline, efficiency, energy efficiency, cache/memory design and I/O design •Greater logic density, power density, wire-ability. All permits more cores per chip, larger cache, additional execution units/circuits, addition of SMT and SIMD on each core. System performance is not linear with frequency ̶Need to use LSPR and z Systems capacity planning tools for real client / workload sizing z Systems leverages advanced technologies to get the most out of chips’ design ̶Low latency pipelines ̶Dense packaging with proper cooling which yields more power-efficient operation ̶Consistent performance at high utilization The IBM z13 ̶z13 is a significant change from zBC12 ̶Processor speed measured in instructions per second (for a given workload) has increased as compared to the zBC12 due to: •Wider pipeline (up to six instructions per cycle) •Enhanced branch prediction •Optimized resolution of dependencies between instructions. •Cache size and design enhancements Processor frequency increase ________________________________ From: IBM Mainframe Discussion List <[email protected]> on behalf of Charles Mills <[email protected]> Sent: 16 April 2025 17:11 To: [email protected] <[email protected]> Subject: Re: z17 If you Google <why processors not getting faster> you will see Reddit and Quora threads going back to about 2010 covering just this topic. I was going to post a link or two but no one article is perfect. They are all oriented (of course!) toward the Intel 486/Pentium/etc. family but chips is chips, more or less. The same physics applies. So if you wish, do your own Googling. The detail reasons have been posted by others. Fast cycle time = more power = more heat = big problem on a small piece of real estate. Size (length of electrical signal), heat dissipation and cycle speed work against each other. Processors actually HAVE been getting faster. The chips are getting faster not in terms of cycle speed but rather in terms of greater parallelism and new instructions that do more in a single cycle. Same for Intel, by the way. The "new instructions" part is why IBM puts so much emphasis on recompiling (or re-sort-of-compiling with the COBOL ABO) existing COBOL applications. The various "do X on condition" instructions (where X is load, store, etc.) that came along a couple of arch levels ago are a great example. They replace (if you code them in HLASM, or let a compiler generate them) the classic compare/branch/load or store sequence. Branches are a parallelism killer because they make the chip consider two different paths. Conditional instructions are not. The vector instructions are a great example of single instructions that do more with their cycles than their predecessors did. Charles On Wed, 16 Apr 2025 08:29:43 -0500, Steve Beaver <[email protected]> wrote: >What I am disappointed in is the CP's have not gone faster than 5.5 Ghz. > >I know the z17 is an evolution, but why have they not gotten faster? ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
