On 7/10/2013 11:54 AM, John Eells wrote:
And, finally, that the branch instruction itself does not stand alone. One must load a register to use it as a base in order to establish addressability, and load another to use it as a displacement register, and Load instructions can cause real memory (vs. cache) accesses. So, it seems to me there can be some applicability to relative branch as well.
Branch prediction is a wonderful thing for optimizing loops and other repetitive branch paths, but it makes it difficult to get meaningful branch benchmarks. Relative branch, in addition to providing relief from the oppressive 4K base register domain, should help a program perform better because:
1. Branch prediction occurs early in the pipeline when there is no access to register contents. With relative branch there is no need for the processor to "waste" time double-checking the branch target address once the contents of the base register are actually known. 2. AGI (address generation interlock) can cause an instruction using a base register to run *brutally* slowly (i.e., stop for a while) if it executes shortly after the base register is loaded. This applies to based branches as well as other types of instructions. Base registers get loaded more often than people think e.g., LM when returning from a subroutine. With relative branch there is ZERO possibility of AGI. 3. Freeing up code base registers for other uses allows program code to be better interleaved by compilers, HLASM programmers that know what they're doing, and OOO execution pipelines on the latest machines.
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