0000000433f07816-dmarc-requ...@listserv.ua.edu (Paul Gilmartin) writes: > How many layers have I neglected? Hercules is a confluent branch.
re: http://www.garlic.com/~lynn/2014m.html#161 Slushware http://www.garlic.com/~lynn/2014m.html#163 Slushware for other hercules drift ... risc processors had performance advantage over intel ... risc having made extensive use of technolology to compensate for the increasing mismatch between memory latency and processor speed ... out-of-order execution, speculative execution, branch-prediction, etc ... sort of the hardware equivalent of '60s multiprogramming to keep processor busy while waiting for disk access (current memory latency, measured in count of cpu cycles is compareable to 60s disk latency when measured in number of 60s cpu cycles). however, for nearly 20yrs, intel has gone to hardware layer that translates intel instructions into risc micro-ops for execution ... largely negating any risc performance advantage. note that somewhat similar (out-of-order, etc) technology started to be introduced for z196 ... claiming it provided over half the performance improvement from z10 to z196 ... and further additions responsible for some of the z196 to ec12 performance improvement. another technology (compensating for stalled instructions) is hyperthreading. I first ran into it when I was asked to help 370/195 for a hyperthreading implementation they wanted to do. 370/195 had pipeline supporting out-of-order execution that could run at 10mips ... but didn't have branch prediction ... so conditional branches would stall the pipeline ... many codes only ran at 5mips. The idea was to simulate multiprocessor operation with two instruction streams, registers ... but still the same pipeline and execution units (two 5mip instruction steams keeping the 10mip execution units busy). note that it dates back to acs/360 in the late 60s ... see multithreading reference near the end of this article http://people.cs.clemson.edu/~mark/acs_end.html also referenced here http://en.wikipedia.org/wiki/Simultaneous_multithreading SPARC T5 can have 8chips/system, 16cores/chip and 128threads/chip (aka 8threads/core) http://en.wikipedia.org/wiki/SPARC_T5 by comparison, about same time as ec12, e5-2600v1 had two 8core chips for 16cores total and 400-600+ BIPS rating (depending on model) ... compared to max configured (101 processors) EC12 @75BIPS. both e5-2600v1 and ec12 processor chips are done in 32nm technology. intel has a tick-tock chip generation http://en.wikipedia.org/wiki/Intel_Tick-Tock alternates shrinking previous chip design with new technology (tick, e5-2600v2 22nm tech) and then designing new chip for the new technology (tock, e5-2600v3 redesign 22nm). some e5-2600v3 (& v4) discussion http://techgadgetnews.com/2014/09/21/intel-xeon-e5-2600-v3-haswell-ep-workstation-and-server-processors-unleashed-for-high-performance-computing/ E5-2690v1 at 632BIPS, E5-2690v2 at 790BIPS, E5-2690v3 at 996BIPS, E5-2699v3 at 1.321TIPS. http://www.tomshardware.com/reviews/intel-xeon-e5-2600-v3-haswell-ep,3932-7.html note MIPS/BIPS/TIPS are benchmark iterations compared to 370/158 assumed to be 1MIP processor. -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
