re: http://www.garlic.com/~lynn/2014m.html#161 Slushware http://www.garlic.com/~lynn/2014m.html#163 Slushware http://www.garlic.com/~lynn/2014m.html#164 Slushware
as an aside ... the hardware layer from i86 instructions to risc micro-ops for execution ... isn't serialized ... it is pipelined operation ... simple version starts with overlapping instruction fetch & decode with instruction execution http://en.wikipedia.org/wiki/Instruction_pipeline the above mentions that pentium4/pentuimD had 31-stage pipeline ... longest in mainstream consumer computing longer pipeline affects the latency for any specific instruction getting executed ... but isn't (necessarily) limiting in the aggregate instruction execution rate (since the operations are overlapped in parallel). there was recent claim (in ibm linkedin discussion) that there is approx. mainframe aggregate 18-20 milllion MIPS in the world today ... or the equivalent of around 270 max. configured EC12s (@75BIPS) ... or about 15 e5-2699v3 blades (@1.3TIPS). A typically cloud megadatacenter can have several hundred thousand blades ... and a standardized virtualization/container facility goes a long way to simplifying the operation. http://www.networkcomputing.com/cloud-infrastructure/virtual-machines-vs-containers-a-matter-of-scope/a/d-id/1269190 -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
